Microprocessors & Microcontrollers interview questions

1. A.transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation
2. B.peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses
3. C.8-bit processor with a 16-bit address bus (64 KB), multiplexed AD0–AD7 lines, five hardware interrupts and 74 instructions
4. D.separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck

Answer + AI explanation with Pro

1. A.NVIC
2. B.8085 interrupt priority
3. C.8085 architecture
4. D.DMA controller

Answer + AI explanation with Pro

1. A.8085 architecture — hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
2. B.8085 architecture — transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation
3. C.8085 architecture — peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses
4. D.8085 architecture — 8-bit processor with a 16-bit address bus (64 KB), multiplexed AD0–AD7 lines, five hardware interrupts and 74 instructions

Answer + AI explanation with Pro

1. A.single chip integrating CPU, RAM, ROM, timers and I/O ports, unlike a microprocessor that needs external memory and peripherals
2. B.nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining
3. C.hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
4. D.separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck

Answer + AI explanation with Pro

1. A.Microcontroller
2. B.NVIC
3. C.DMA controller
4. D.Harvard architecture

Answer + AI explanation with Pro

1. A.Microcontroller — Harvard-style separation with 4 KB on-chip program ROM, 128 bytes of data RAM, four 8-bit ports and two 16-bit timers
2. B.Microcontroller — hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
3. C.Microcontroller — single chip integrating CPU, RAM, ROM, timers and I/O ports, unlike a microprocessor that needs external memory and peripherals
4. D.Microcontroller — TRAP is non-maskable and highest, followed by RST 7.5, RST 6.5, RST 5.5 and INTR in descending order

Answer + AI explanation with Pro

1. A.hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
2. B.8-bit processor with a 16-bit address bus (64 KB), multiplexed AD0–AD7 lines, five hardware interrupts and 74 instructions
3. C.Harvard-style separation with 4 KB on-chip program ROM, 128 bytes of data RAM, four 8-bit ports and two 16-bit timers
4. D.separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck

Answer + AI explanation with Pro

1. A.8051 memory organisation
2. B.NVIC
3. C.Microcontroller
4. D.Watchdog timer

Answer + AI explanation with Pro

1. A.8051 memory organisation — nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining
2. B.8051 memory organisation — transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation
3. C.8051 memory organisation — Harvard-style separation with 4 KB on-chip program ROM, 128 bytes of data RAM, four 8-bit ports and two 16-bit timers
4. D.8051 memory organisation — separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck

Answer + AI explanation with Pro

1. A.TRAP is non-maskable and highest, followed by RST 7.5, RST 6.5, RST 5.5 and INTR in descending order
2. B.nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining
3. C.single chip integrating CPU, RAM, ROM, timers and I/O ports, unlike a microprocessor that needs external memory and peripherals
4. D.transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation

Answer + AI explanation with Pro

1. A.Microcontroller
2. B.Watchdog timer
3. C.NVIC
4. D.8085 interrupt priority

Answer + AI explanation with Pro

1. A.8085 interrupt priority — TRAP is non-maskable and highest, followed by RST 7.5, RST 6.5, RST 5.5 and INTR in descending order
2. B.8085 interrupt priority — nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining
3. C.8085 interrupt priority — hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
4. D.8085 interrupt priority — separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck

Answer + AI explanation with Pro

1. A.transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation
2. B.single chip integrating CPU, RAM, ROM, timers and I/O ports, unlike a microprocessor that needs external memory and peripherals
3. C.separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck
4. D.peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses

Answer + AI explanation with Pro

1. A.NVIC
2. B.Harvard architecture
3. C.8085 architecture
4. D.Memory-mapped I/O

Answer + AI explanation with Pro

1. A.Memory-mapped I/O — nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining
2. B.Memory-mapped I/O — Harvard-style separation with 4 KB on-chip program ROM, 128 bytes of data RAM, four 8-bit ports and two 16-bit timers
3. C.Memory-mapped I/O — transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation
4. D.Memory-mapped I/O — peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses

Answer + AI explanation with Pro

1. A.Harvard-style separation with 4 KB on-chip program ROM, 128 bytes of data RAM, four 8-bit ports and two 16-bit timers
2. B.hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
3. C.nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining
4. D.8-bit processor with a 16-bit address bus (64 KB), multiplexed AD0–AD7 lines, five hardware interrupts and 74 instructions

Answer + AI explanation with Pro

1. A.Watchdog timer
2. B.8051 memory organisation
3. C.8085 architecture
4. D.DMA controller

Answer + AI explanation with Pro

1. A.Watchdog timer — hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
2. B.Watchdog timer — nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining
3. C.Watchdog timer — TRAP is non-maskable and highest, followed by RST 7.5, RST 6.5, RST 5.5 and INTR in descending order
4. D.Watchdog timer — separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck

Answer + AI explanation with Pro

1. A.peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses
2. B.8-bit processor with a 16-bit address bus (64 KB), multiplexed AD0–AD7 lines, five hardware interrupts and 74 instructions
3. C.nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining
4. D.separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck

Answer + AI explanation with Pro

1. A.NVIC
2. B.Harvard architecture
3. C.Watchdog timer
4. D.8085 interrupt priority

Answer + AI explanation with Pro

1. A.Harvard architecture — hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
2. B.Harvard architecture — single chip integrating CPU, RAM, ROM, timers and I/O ports, unlike a microprocessor that needs external memory and peripherals
3. C.Harvard architecture — separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck
4. D.Harvard architecture — Harvard-style separation with 4 KB on-chip program ROM, 128 bytes of data RAM, four 8-bit ports and two 16-bit timers

Answer + AI explanation with Pro

1. A.hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
2. B.separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck
3. C.transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation
4. D.nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining

Answer + AI explanation with Pro

1. A.NVIC
2. B.8051 memory organisation
3. C.8085 interrupt priority
4. D.Harvard architecture

Answer + AI explanation with Pro

1. A.NVIC — Harvard-style separation with 4 KB on-chip program ROM, 128 bytes of data RAM, four 8-bit ports and two 16-bit timers
2. B.NVIC — hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
3. C.NVIC — peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses
4. D.NVIC — nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining

Answer + AI explanation with Pro

1. A.single chip integrating CPU, RAM, ROM, timers and I/O ports, unlike a microprocessor that needs external memory and peripherals
2. B.peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses
3. C.transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation
4. D.separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck

Answer + AI explanation with Pro

1. A.Harvard architecture
2. B.NVIC
3. C.DMA controller
4. D.8085 architecture

Answer + AI explanation with Pro

1. A.DMA controller — separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck
2. B.DMA controller — hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
3. C.DMA controller — transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation
4. D.DMA controller — peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses

Answer + AI explanation with Pro