Communication Protocols interview questions

1. A.master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
2. B.asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
3. C.differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing
4. D.two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed

Answer + AI explanation with Pro

1. A.Modbus RTU
2. B.USB enumeration
3. C.UART framing
4. D.CAN arbitration

Answer + AI explanation with Pro

1. A.UART framing — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
2. B.UART framing — asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
3. C.UART framing — single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
4. D.UART framing — host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver

Answer + AI explanation with Pro

1. A.master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
2. B.single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
3. C.CRC, bit-stuffing, form and ACK checks raise error frames, and transmit/receive error counters move a node to error-passive at 128 and bus-off at 256
4. D.synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA

Answer + AI explanation with Pro

1. A.CAN error handling
2. B.SPI
3. C.UART framing
4. D.RS-485

Answer + AI explanation with Pro

1. A.SPI — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
2. B.SPI — CRC, bit-stuffing, form and ACK checks raise error frames, and transmit/receive error counters move a node to error-passive at 128 and bus-off at 256
3. C.SPI — single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
4. D.SPI — two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed

Answer + AI explanation with Pro

1. A.single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
2. B.synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
3. C.master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
4. D.two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed

Answer + AI explanation with Pro

1. A.SPI
2. B.RS-485
3. C.LIN
4. D.I2C

Answer + AI explanation with Pro

1. A.I2C — single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
2. B.I2C — two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
3. C.I2C — master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
4. D.I2C — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA

Answer + AI explanation with Pro

1. A.differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing
2. B.two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
3. C.master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
4. D.bitwise non-destructive contest on the identifier where a dominant 0 beats a recessive 1, so the lowest ID wins without losing time, at up to 1 Mbit/s classic or 8 Mbit/s CAN FD data phase

Answer + AI explanation with Pro

1. A.CAN arbitration
2. B.UART framing
3. C.Modbus RTU
4. D.CAN error handling

Answer + AI explanation with Pro

1. A.CAN arbitration — bitwise non-destructive contest on the identifier where a dominant 0 beats a recessive 1, so the lowest ID wins without losing time, at up to 1 Mbit/s classic or 8 Mbit/s CAN FD data phase
2. B.CAN arbitration — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
3. C.CAN arbitration — asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
4. D.CAN arbitration — host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver

Answer + AI explanation with Pro

1. A.differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing
2. B.synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
3. C.CRC, bit-stuffing, form and ACK checks raise error frames, and transmit/receive error counters move a node to error-passive at 128 and bus-off at 256
4. D.asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%

Answer + AI explanation with Pro

1. A.RS-485
2. B.LIN
3. C.CAN arbitration
4. D.UART framing

Answer + AI explanation with Pro

1. A.RS-485 — asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
2. B.RS-485 — two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
3. C.RS-485 — single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
4. D.RS-485 — differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing

Answer + AI explanation with Pro

1. A.single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
2. B.host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver
3. C.master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
4. D.synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA

Answer + AI explanation with Pro

1. A.SPI
2. B.CAN error handling
3. C.CAN arbitration
4. D.Modbus RTU

Answer + AI explanation with Pro

1. A.Modbus RTU — two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
2. B.Modbus RTU — host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver
3. C.Modbus RTU — single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
4. D.Modbus RTU — master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames

Answer + AI explanation with Pro

1. A.asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
2. B.single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
3. C.host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver
4. D.differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing

Answer + AI explanation with Pro

1. A.LIN
2. B.I2C
3. C.RS-485
4. D.CAN arbitration

Answer + AI explanation with Pro

1. A.LIN — differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing
2. B.LIN — single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
3. C.LIN — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
4. D.LIN — two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed

Answer + AI explanation with Pro

1. A.host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver
2. B.differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing
3. C.asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
4. D.single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame

Answer + AI explanation with Pro

1. A.UART framing
2. B.USB enumeration
3. C.SPI
4. D.I2C

Answer + AI explanation with Pro

1. A.USB enumeration — bitwise non-destructive contest on the identifier where a dominant 0 beats a recessive 1, so the lowest ID wins without losing time, at up to 1 Mbit/s classic or 8 Mbit/s CAN FD data phase
2. B.USB enumeration — CRC, bit-stuffing, form and ACK checks raise error frames, and transmit/receive error counters move a node to error-passive at 128 and bus-off at 256
3. C.USB enumeration — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
4. D.USB enumeration — host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver

Answer + AI explanation with Pro

1. A.single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
2. B.two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
3. C.CRC, bit-stuffing, form and ACK checks raise error frames, and transmit/receive error counters move a node to error-passive at 128 and bus-off at 256
4. D.master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames

Answer + AI explanation with Pro

1. A.RS-485
2. B.SPI
3. C.I2C
4. D.CAN error handling

Answer + AI explanation with Pro

1. A.CAN error handling — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
2. B.CAN error handling — CRC, bit-stuffing, form and ACK checks raise error frames, and transmit/receive error counters move a node to error-passive at 128 and bus-off at 256
3. C.CAN error handling — bitwise non-destructive contest on the identifier where a dominant 0 beats a recessive 1, so the lowest ID wins without losing time, at up to 1 Mbit/s classic or 8 Mbit/s CAN FD data phase
4. D.CAN error handling — asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%

Answer + AI explanation with Pro