Power & Signal Integrity interview questions

1. A.shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
2. B.small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
3. C.series resistor at the driver or parallel or Thevenin resistor at the receiver absorbing reflections once trace delay exceeds about one-sixth of the signal rise time
4. D.trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations

Answer + AI explanation with Pro

1. A.Termination
2. B.Power delivery network impedance
3. C.Decoupling capacitors
4. D.LDO versus SMPS

Answer + AI explanation with Pro

1. A.Decoupling capacitors — shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
2. B.Decoupling capacitors — small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
3. C.Decoupling capacitors — residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
4. D.Decoupling capacitors — linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count

Answer + AI explanation with Pro

1. A.linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
2. B.small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
3. C.transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
4. D.trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations

Answer + AI explanation with Pro

1. A.LDO versus SMPS
2. B.Decoupling capacitors
3. C.Termination
4. D.Controlled impedance

Answer + AI explanation with Pro

1. A.LDO versus SMPS — trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
2. B.LDO versus SMPS — shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
3. C.LDO versus SMPS — linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
4. D.LDO versus SMPS — series resistor at the driver or parallel or Thevenin resistor at the receiver absorbing reflections once trace delay exceeds about one-sixth of the signal rise time

Answer + AI explanation with Pro

1. A.small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
2. B.shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
3. C.transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
4. D.residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator

Answer + AI explanation with Pro

1. A.Power delivery network impedance
2. B.Output ripple
3. C.Decoupling capacitors
4. D.Controlled impedance

Answer + AI explanation with Pro

1. A.Output ripple — residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
2. B.Output ripple — series resistor at the driver or parallel or Thevenin resistor at the receiver absorbing reflections once trace delay exceeds about one-sixth of the signal rise time
3. C.Output ripple — coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
4. D.Output ripple — small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail

Answer + AI explanation with Pro

1. A.shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
2. B.linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
3. C.trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
4. D.target Z = ΔV/ΔI held across frequency by combining bulk, ceramic and on-die capacitance so anti-resonance peaks between them stay below the limit

Answer + AI explanation with Pro

1. A.LDO versus SMPS
2. B.Termination
3. C.Power delivery network impedance
4. D.Controlled impedance

Answer + AI explanation with Pro

1. A.Controlled impedance — trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
2. B.Controlled impedance — transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
3. C.Controlled impedance — residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
4. D.Controlled impedance — target Z = ΔV/ΔI held across frequency by combining bulk, ceramic and on-die capacitance so anti-resonance peaks between them stay below the limit

Answer + AI explanation with Pro

1. A.coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
2. B.linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
3. C.trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
4. D.shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs

Answer + AI explanation with Pro

1. A.Crosstalk
2. B.Ground bounce
3. C.Power delivery network impedance
4. D.Controlled impedance

Answer + AI explanation with Pro

1. A.Crosstalk — residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
2. B.Crosstalk — transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
3. C.Crosstalk — linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
4. D.Crosstalk — coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference

Answer + AI explanation with Pro

1. A.linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
2. B.small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
3. C.series resistor at the driver or parallel or Thevenin resistor at the receiver absorbing reflections once trace delay exceeds about one-sixth of the signal rise time
4. D.coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference

Answer + AI explanation with Pro

1. A.Termination
2. B.ESD and TVS protection
3. C.LDO versus SMPS
4. D.Decoupling capacitors

Answer + AI explanation with Pro

1. A.Termination — trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
2. B.Termination — residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
3. C.Termination — series resistor at the driver or parallel or Thevenin resistor at the receiver absorbing reflections once trace delay exceeds about one-sixth of the signal rise time
4. D.Termination — transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports

Answer + AI explanation with Pro

1. A.trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
2. B.shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
3. C.coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
4. D.transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports

Answer + AI explanation with Pro

1. A.Power delivery network impedance
2. B.Termination
3. C.Ground bounce
4. D.Decoupling capacitors

Answer + AI explanation with Pro

1. A.Ground bounce — residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
2. B.Ground bounce — shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
3. C.Ground bounce — coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
4. D.Ground bounce — linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count

Answer + AI explanation with Pro

1. A.series resistor at the driver or parallel or Thevenin resistor at the receiver absorbing reflections once trace delay exceeds about one-sixth of the signal rise time
2. B.transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
3. C.coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
4. D.target Z = ΔV/ΔI held across frequency by combining bulk, ceramic and on-die capacitance so anti-resonance peaks between them stay below the limit

Answer + AI explanation with Pro

1. A.Power delivery network impedance
2. B.Output ripple
3. C.ESD and TVS protection
4. D.Decoupling capacitors

Answer + AI explanation with Pro

1. A.ESD and TVS protection — transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
2. B.ESD and TVS protection — target Z = ΔV/ΔI held across frequency by combining bulk, ceramic and on-die capacitance so anti-resonance peaks between them stay below the limit
3. C.ESD and TVS protection — small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
4. D.ESD and TVS protection — shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs

Answer + AI explanation with Pro

1. A.target Z = ΔV/ΔI held across frequency by combining bulk, ceramic and on-die capacitance so anti-resonance peaks between them stay below the limit
2. B.residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
3. C.transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
4. D.trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations

Answer + AI explanation with Pro

1. A.Termination
2. B.Controlled impedance
3. C.ESD and TVS protection
4. D.Power delivery network impedance

Answer + AI explanation with Pro

1. A.Power delivery network impedance — transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
2. B.Power delivery network impedance — small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
3. C.Power delivery network impedance — coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
4. D.Power delivery network impedance — target Z = ΔV/ΔI held across frequency by combining bulk, ceramic and on-die capacitance so anti-resonance peaks between them stay below the limit

Answer + AI explanation with Pro