Digital Electronics interview questions

1. A.asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
2. B.NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
3. C.in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction
4. D.combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables

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1. A.Ripple versus synchronous counter
2. B.Successive approximation ADC
3. C.Universal gates
4. D.SRAM versus DRAM

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1. A.Universal gates — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
2. B.Universal gates — NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
3. C.Universal gates — Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
4. D.Universal gates — converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input

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1. A.asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
2. B.Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
3. C.flip-flop state where the output hovers between logic levels for an unbounded time after a setup or hold violation, mitigated by two-stage synchronisers on asynchronous inputs
4. D.complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms

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1. A.Metastability
2. B.De Morgan's theorems
3. C.Universal gates
4. D.Race-around condition

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1. A.De Morgan's theorems — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
2. B.De Morgan's theorems — flip-flop state where the output hovers between logic levels for an unbounded time after a setup or hold violation, mitigated by two-stage synchronisers on asynchronous inputs
3. C.De Morgan's theorems — Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
4. D.De Morgan's theorems — combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables

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1. A.Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
2. B.complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
3. C.asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
4. D.combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables

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1. A.De Morgan's theorems
2. B.Race-around condition
3. C.Mealy versus Moore machine
4. D.Multiplexer

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1. A.Multiplexer — Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
2. B.Multiplexer — combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
3. C.Multiplexer — asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
4. D.Multiplexer — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms

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1. A.in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction
2. B.combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
3. C.asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
4. D.static cell of six transistors holds data without refresh and is fast; dynamic cell of one transistor and one capacitor is denser and cheaper but needs periodic refresh

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1. A.SRAM versus DRAM
2. B.Universal gates
3. C.Ripple versus synchronous counter
4. D.Metastability

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1. A.SRAM versus DRAM — static cell of six transistors holds data without refresh and is fast; dynamic cell of one transistor and one capacitor is denser and cheaper but needs periodic refresh
2. B.SRAM versus DRAM — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
3. C.SRAM versus DRAM — NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
4. D.SRAM versus DRAM — converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input

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1. A.in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction
2. B.complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
3. C.flip-flop state where the output hovers between logic levels for an unbounded time after a setup or hold violation, mitigated by two-stage synchronisers on asynchronous inputs
4. D.NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type

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1. A.Race-around condition
2. B.Mealy versus Moore machine
3. C.SRAM versus DRAM
4. D.Universal gates

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1. A.Race-around condition — NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
2. B.Race-around condition — combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
3. C.Race-around condition — Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
4. D.Race-around condition — in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction

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1. A.Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
2. B.converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input
3. C.asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
4. D.complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms

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1. A.De Morgan's theorems
2. B.Metastability
3. C.SRAM versus DRAM
4. D.Ripple versus synchronous counter

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1. A.Ripple versus synchronous counter — combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
2. B.Ripple versus synchronous counter — converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input
3. C.Ripple versus synchronous counter — Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
4. D.Ripple versus synchronous counter — asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count

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1. A.NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
2. B.Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
3. C.converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input
4. D.in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction

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1. A.Mealy versus Moore machine
2. B.Multiplexer
3. C.Race-around condition
4. D.SRAM versus DRAM

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1. A.Mealy versus Moore machine — in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction
2. B.Mealy versus Moore machine — Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
3. C.Mealy versus Moore machine — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
4. D.Mealy versus Moore machine — combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables

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1. A.converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input
2. B.in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction
3. C.NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
4. D.Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change

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1. A.Universal gates
2. B.Successive approximation ADC
3. C.De Morgan's theorems
4. D.Multiplexer

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1. A.Successive approximation ADC — static cell of six transistors holds data without refresh and is fast; dynamic cell of one transistor and one capacitor is denser and cheaper but needs periodic refresh
2. B.Successive approximation ADC — flip-flop state where the output hovers between logic levels for an unbounded time after a setup or hold violation, mitigated by two-stage synchronisers on asynchronous inputs
3. C.Successive approximation ADC — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
4. D.Successive approximation ADC — converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input

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1. A.Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
2. B.combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
3. C.flip-flop state where the output hovers between logic levels for an unbounded time after a setup or hold violation, mitigated by two-stage synchronisers on asynchronous inputs
4. D.asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count

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1. A.Race-around condition
2. B.De Morgan's theorems
3. C.Multiplexer
4. D.Metastability

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1. A.Metastability — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
2. B.Metastability — flip-flop state where the output hovers between logic levels for an unbounded time after a setup or hold violation, mitigated by two-stage synchronisers on asynchronous inputs
3. C.Metastability — static cell of six transistors holds data without refresh and is fast; dynamic cell of one transistor and one capacitor is denser and cheaper but needs periodic refresh
4. D.Metastability — NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type

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