27 Microprocessors & Microcontrollers questions from the ECE Core bank, written for Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd.
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A.open-drain bidirectional port needing external pull-ups, also multiplexing the low address and data bytes for external memory access
B.five status bits Sign, Zero, Auxiliary Carry, Parity and Carry, updated by arithmetic and logic instructions and tested by conditional jumps
C.32-bit RISC core where only load and store instructions access memory, using Thumb-2 mixed 16- and 32-bit encoding for code density
D.address latch enable pulse issued in T1 of every 8085 machine cycle to capture the low address byte from the multiplexed AD0–AD7 lines into an external latch
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2. Which term means: "five status bits Sign, Zero, Auxiliary Carry, Parity and Carry, updated by arithmetic and logic instructions and tested by conditional jumps"?
Junior
A.Cortex-M load-store architecture
B.8085 flag register
C.BIU and EU pipelining
D.8085 machine cycles
Answer + AI explanation with Pro
3. Which statement is correct?
Junior
A.8085 flag register — 8086 bus interface unit prefetches up to six instruction bytes into a queue while the execution unit runs, overlapping fetch and execute
B.8085 flag register — five status bits Sign, Zero, Auxiliary Carry, Parity and Carry, updated by arithmetic and logic instructions and tested by conditional jumps
C.8085 flag register — 20-bit physical address formed as segment × 16 + offset, covering 1 MB through four 64 KB segments CS, DS, SS and ES
D.8085 flag register — open-drain bidirectional port needing external pull-ups, also multiplexing the low address and data bytes for external memory access
Answer + AI explanation with Pro
4. What is 8086 segmented memory?
Junior
A.address latch enable pulse issued in T1 of every 8085 machine cycle to capture the low address byte from the multiplexed AD0–AD7 lines into an external latch
B.20-bit physical address formed as segment × 16 + offset, covering 1 MB through four 64 KB segments CS, DS, SS and ES
C.five status bits Sign, Zero, Auxiliary Carry, Parity and Carry, updated by arithmetic and logic instructions and tested by conditional jumps
D.8086 bus interface unit prefetches up to six instruction bytes into a queue while the execution unit runs, overlapping fetch and execute
Answer + AI explanation with Pro
5. Which term means: "20-bit physical address formed as segment × 16 + offset, covering 1 MB through four 64 KB segments CS, DS, SS and ES"?
Junior
A.ALE signal
B.BIU and EU pipelining
C.8085 flag register
D.8086 segmented memory
Answer + AI explanation with Pro
6. Which statement is correct?
Junior
A.8086 segmented memory — opcode fetch takes four T-states (six for some instructions), memory read or write takes three, each T-state being one clock period
B.8086 segmented memory — address latch enable pulse issued in T1 of every 8085 machine cycle to capture the low address byte from the multiplexed AD0–AD7 lines into an external latch
C.8086 segmented memory — hardware automatically pushes R0–R3, R12, LR, PC and xPSR onto the stack so handlers are ordinary C functions, with tail-chaining between back-to-back interrupts
D.8086 segmented memory — 20-bit physical address formed as segment × 16 + offset, covering 1 MB through four 64 KB segments CS, DS, SS and ES
Answer + AI explanation with Pro
7. What is 8051 Port 0?
Junior
A.20-bit physical address formed as segment × 16 + offset, covering 1 MB through four 64 KB segments CS, DS, SS and ES
B.open-drain bidirectional port needing external pull-ups, also multiplexing the low address and data bytes for external memory access
C.hardware automatically pushes R0–R3, R12, LR, PC and xPSR onto the stack so handlers are ordinary C functions, with tail-chaining between back-to-back interrupts
D.five status bits Sign, Zero, Auxiliary Carry, Parity and Carry, updated by arithmetic and logic instructions and tested by conditional jumps
Answer + AI explanation with Pro
8. Which term means: "open-drain bidirectional port needing external pull-ups, also multiplexing the low address and data bytes for external memory access"?
Junior
A.8051 interrupt structure
B.8086 segmented memory
C.Cortex-M load-store architecture
D.8051 Port 0
Answer + AI explanation with Pro
9. Which statement is correct?
Junior
A.8051 Port 0 — 32-bit RISC core where only load and store instructions access memory, using Thumb-2 mixed 16- and 32-bit encoding for code density
B.8051 Port 0 — five sources INT0, Timer 0, INT1, Timer 1 and serial, two programmable priority levels via IP, with vectors eight bytes apart starting at 0003H
C.8051 Port 0 — hardware automatically pushes R0–R3, R12, LR, PC and xPSR onto the stack so handlers are ordinary C functions, with tail-chaining between back-to-back interrupts
D.8051 Port 0 — open-drain bidirectional port needing external pull-ups, also multiplexing the low address and data bytes for external memory access
Answer + AI explanation with Pro
10. What is ALE signal?
Junior
A.hardware automatically pushes R0–R3, R12, LR, PC and xPSR onto the stack so handlers are ordinary C functions, with tail-chaining between back-to-back interrupts
B.32-bit RISC core where only load and store instructions access memory, using Thumb-2 mixed 16- and 32-bit encoding for code density
C.20-bit physical address formed as segment × 16 + offset, covering 1 MB through four 64 KB segments CS, DS, SS and ES
D.address latch enable pulse issued in T1 of every 8085 machine cycle to capture the low address byte from the multiplexed AD0–AD7 lines into an external latch
Answer + AI explanation with Pro
11. Which term means: "address latch enable pulse issued in T1 of every 8085 machine cycle to capture the low address byte from the multiplexed AD0–AD7 lines into an external latch"?
Junior
A.8085 machine cycles
B.Cortex-M load-store architecture
C.ALE signal
D.8051 Port 0
Answer + AI explanation with Pro
12. Which statement is correct?
Junior
A.ALE signal — five status bits Sign, Zero, Auxiliary Carry, Parity and Carry, updated by arithmetic and logic instructions and tested by conditional jumps
B.ALE signal — five sources INT0, Timer 0, INT1, Timer 1 and serial, two programmable priority levels via IP, with vectors eight bytes apart starting at 0003H
C.ALE signal — 8086 bus interface unit prefetches up to six instruction bytes into a queue while the execution unit runs, overlapping fetch and execute
D.ALE signal — address latch enable pulse issued in T1 of every 8085 machine cycle to capture the low address byte from the multiplexed AD0–AD7 lines into an external latch
Answer + AI explanation with Pro
13. What is BIU and EU pipelining?
Mid
A.five status bits Sign, Zero, Auxiliary Carry, Parity and Carry, updated by arithmetic and logic instructions and tested by conditional jumps
B.8086 bus interface unit prefetches up to six instruction bytes into a queue while the execution unit runs, overlapping fetch and execute
C.address latch enable pulse issued in T1 of every 8085 machine cycle to capture the low address byte from the multiplexed AD0–AD7 lines into an external latch
D.hardware automatically pushes R0–R3, R12, LR, PC and xPSR onto the stack so handlers are ordinary C functions, with tail-chaining between back-to-back interrupts
Answer + AI explanation with Pro
14. Which term means: "8086 bus interface unit prefetches up to six instruction bytes into a queue while the execution unit runs, overlapping fetch and execute"?
Mid
A.ALE signal
B.BIU and EU pipelining
C.8051 Port 0
D.8086 segmented memory
Answer + AI explanation with Pro
15. Which statement is correct?
Mid
A.BIU and EU pipelining — five sources INT0, Timer 0, INT1, Timer 1 and serial, two programmable priority levels via IP, with vectors eight bytes apart starting at 0003H
B.BIU and EU pipelining — 32-bit RISC core where only load and store instructions access memory, using Thumb-2 mixed 16- and 32-bit encoding for code density
C.BIU and EU pipelining — address latch enable pulse issued in T1 of every 8085 machine cycle to capture the low address byte from the multiplexed AD0–AD7 lines into an external latch
D.BIU and EU pipelining — 8086 bus interface unit prefetches up to six instruction bytes into a queue while the execution unit runs, overlapping fetch and execute
Answer + AI explanation with Pro
16. What is 8085 machine cycles?
Mid
A.opcode fetch takes four T-states (six for some instructions), memory read or write takes three, each T-state being one clock period
B.hardware automatically pushes R0–R3, R12, LR, PC and xPSR onto the stack so handlers are ordinary C functions, with tail-chaining between back-to-back interrupts
C.five status bits Sign, Zero, Auxiliary Carry, Parity and Carry, updated by arithmetic and logic instructions and tested by conditional jumps
D.open-drain bidirectional port needing external pull-ups, also multiplexing the low address and data bytes for external memory access
Answer + AI explanation with Pro
17. Which term means: "opcode fetch takes four T-states (six for some instructions), memory read or write takes three, each T-state being one clock period"?
Mid
A.ALE signal
B.8085 flag register
C.8085 machine cycles
D.Cortex-M exception entry
Answer + AI explanation with Pro
18. Which statement is correct?
Mid
A.8085 machine cycles — 8086 bus interface unit prefetches up to six instruction bytes into a queue while the execution unit runs, overlapping fetch and execute
B.8085 machine cycles — 32-bit RISC core where only load and store instructions access memory, using Thumb-2 mixed 16- and 32-bit encoding for code density
C.8085 machine cycles — opcode fetch takes four T-states (six for some instructions), memory read or write takes three, each T-state being one clock period
D.8085 machine cycles — five sources INT0, Timer 0, INT1, Timer 1 and serial, two programmable priority levels via IP, with vectors eight bytes apart starting at 0003H
Answer + AI explanation with Pro
19. What is 8051 interrupt structure?
Mid
A.five status bits Sign, Zero, Auxiliary Carry, Parity and Carry, updated by arithmetic and logic instructions and tested by conditional jumps
B.five sources INT0, Timer 0, INT1, Timer 1 and serial, two programmable priority levels via IP, with vectors eight bytes apart starting at 0003H
C.open-drain bidirectional port needing external pull-ups, also multiplexing the low address and data bytes for external memory access
D.opcode fetch takes four T-states (six for some instructions), memory read or write takes three, each T-state being one clock period
Answer + AI explanation with Pro
20. Which term means: "five sources INT0, Timer 0, INT1, Timer 1 and serial, two programmable priority levels via IP, with vectors eight bytes apart starting at 0003H"?
Mid
A.ALE signal
B.8051 interrupt structure
C.BIU and EU pipelining
D.8085 flag register
Answer + AI explanation with Pro
21. Which statement is correct?
Mid
A.8051 interrupt structure — five sources INT0, Timer 0, INT1, Timer 1 and serial, two programmable priority levels via IP, with vectors eight bytes apart starting at 0003H
B.8051 interrupt structure — 20-bit physical address formed as segment × 16 + offset, covering 1 MB through four 64 KB segments CS, DS, SS and ES
C.8051 interrupt structure — five status bits Sign, Zero, Auxiliary Carry, Parity and Carry, updated by arithmetic and logic instructions and tested by conditional jumps
D.8051 interrupt structure — address latch enable pulse issued in T1 of every 8085 machine cycle to capture the low address byte from the multiplexed AD0–AD7 lines into an external latch
Answer + AI explanation with Pro
22. What is Cortex-M load-store architecture?
Mid
A.address latch enable pulse issued in T1 of every 8085 machine cycle to capture the low address byte from the multiplexed AD0–AD7 lines into an external latch
B.open-drain bidirectional port needing external pull-ups, also multiplexing the low address and data bytes for external memory access
C.five status bits Sign, Zero, Auxiliary Carry, Parity and Carry, updated by arithmetic and logic instructions and tested by conditional jumps
D.32-bit RISC core where only load and store instructions access memory, using Thumb-2 mixed 16- and 32-bit encoding for code density
Answer + AI explanation with Pro
23. Which term means: "32-bit RISC core where only load and store instructions access memory, using Thumb-2 mixed 16- and 32-bit encoding for code density"?
Mid
A.8086 segmented memory
B.8051 interrupt structure
C.Cortex-M load-store architecture
D.Cortex-M exception entry
Answer + AI explanation with Pro
24. Which statement is correct?
Mid
A.Cortex-M load-store architecture — 32-bit RISC core where only load and store instructions access memory, using Thumb-2 mixed 16- and 32-bit encoding for code density
B.Cortex-M load-store architecture — open-drain bidirectional port needing external pull-ups, also multiplexing the low address and data bytes for external memory access
C.Cortex-M load-store architecture — opcode fetch takes four T-states (six for some instructions), memory read or write takes three, each T-state being one clock period
D.Cortex-M load-store architecture — address latch enable pulse issued in T1 of every 8085 machine cycle to capture the low address byte from the multiplexed AD0–AD7 lines into an external latch
Answer + AI explanation with Pro
25. What is Cortex-M exception entry?
Senior
A.five status bits Sign, Zero, Auxiliary Carry, Parity and Carry, updated by arithmetic and logic instructions and tested by conditional jumps
B.20-bit physical address formed as segment × 16 + offset, covering 1 MB through four 64 KB segments CS, DS, SS and ES
C.8086 bus interface unit prefetches up to six instruction bytes into a queue while the execution unit runs, overlapping fetch and execute
D.hardware automatically pushes R0–R3, R12, LR, PC and xPSR onto the stack so handlers are ordinary C functions, with tail-chaining between back-to-back interrupts
Answer + AI explanation with Pro
26. Which term means: "hardware automatically pushes R0–R3, R12, LR, PC and xPSR onto the stack so handlers are ordinary C functions, with tail-chaining between back-to-back interrupts"?
Senior
A.8085 flag register
B.Cortex-M exception entry
C.8085 machine cycles
D.8051 interrupt structure
Answer + AI explanation with Pro
27. Which statement is correct?
Senior
A.Cortex-M exception entry — 8086 bus interface unit prefetches up to six instruction bytes into a queue while the execution unit runs, overlapping fetch and execute
B.Cortex-M exception entry — hardware automatically pushes R0–R3, R12, LR, PC and xPSR onto the stack so handlers are ordinary C functions, with tail-chaining between back-to-back interrupts
C.Cortex-M exception entry — five sources INT0, Timer 0, INT1, Timer 1 and serial, two programmable priority levels via IP, with vectors eight bytes apart starting at 0003H
D.Cortex-M exception entry — five status bits Sign, Zero, Auxiliary Carry, Parity and Carry, updated by arithmetic and logic instructions and tested by conditional jumps
Answer + AI explanation with Pro
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