Semiconductor Devices interview questions

1. A.undoped crystal with equal electron and hole concentrations, about 1.5×10^10 per cm³ for silicon at 300 K, and a Fermi level near mid-gap
2. B.zone on either side of a PN junction emptied of mobile carriers and containing fixed ionised dopants, narrowing under forward bias and widening under reverse bias
3. C.patterning step exposing photoresist through a mask, with minimum feature size k1·λ/NA, pushed to 13.5 nm EUV for leading-edge nodes
4. D.junction barrier (kT/q)·ln(NA·ND/ni²), about 0.6–0.7 V for silicon, which cannot be measured with an external voltmeter because contact potentials cancel it

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1. A.Ion implantation
2. B.Intrinsic semiconductor
3. C.Energy band gap
4. D.MOSFET threshold voltage

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1. A.Intrinsic semiconductor — undoped crystal with equal electron and hole concentrations, about 1.5×10^10 per cm³ for silicon at 300 K, and a Fermi level near mid-gap
2. B.Intrinsic semiconductor — separation between valence and conduction bands, 1.12 eV for silicon, 0.67 eV for germanium and 1.42 eV for GaAs at room temperature
3. C.Intrinsic semiconductor — tunnelling in heavily doped junctions below about 5 V with negative temperature coefficient, versus impact ionisation above about 6 V with positive coefficient
4. D.Intrinsic semiconductor — zone on either side of a PN junction emptied of mobile carriers and containing fixed ionised dopants, narrowing under forward bias and widening under reverse bias

Answer + AI explanation with Pro

1. A.drift is carrier motion under an electric field, diffusion is motion from high to low concentration; both are linked through the Einstein relation D/μ = kT/q
2. B.doping by accelerating ions into the wafer, giving precise dose and depth control at low temperature but requiring an anneal to repair lattice damage, unlike isotropic thermal diffusion
3. C.gate voltage at which strong inversion begins with surface potential about 2φF, set by oxide thickness, substrate doping and flat-band voltage
4. D.separation between valence and conduction bands, 1.12 eV for silicon, 0.67 eV for germanium and 1.42 eV for GaAs at room temperature

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1. A.Intrinsic semiconductor
2. B.Ion implantation
3. C.Energy band gap
4. D.MOSFET threshold voltage

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1. A.Energy band gap — zone on either side of a PN junction emptied of mobile carriers and containing fixed ionised dopants, narrowing under forward bias and widening under reverse bias
2. B.Energy band gap — drift is carrier motion under an electric field, diffusion is motion from high to low concentration; both are linked through the Einstein relation D/μ = kT/q
3. C.Energy band gap — tunnelling in heavily doped junctions below about 5 V with negative temperature coefficient, versus impact ionisation above about 6 V with positive coefficient
4. D.Energy band gap — separation between valence and conduction bands, 1.12 eV for silicon, 0.67 eV for germanium and 1.42 eV for GaAs at room temperature

Answer + AI explanation with Pro

1. A.gate voltage at which strong inversion begins with surface potential about 2φF, set by oxide thickness, substrate doping and flat-band voltage
2. B.undoped crystal with equal electron and hole concentrations, about 1.5×10^10 per cm³ for silicon at 300 K, and a Fermi level near mid-gap
3. C.patterning step exposing photoresist through a mask, with minimum feature size k1·λ/NA, pushed to 13.5 nm EUV for leading-edge nodes
4. D.zone on either side of a PN junction emptied of mobile carriers and containing fixed ionised dopants, narrowing under forward bias and widening under reverse bias

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1. A.Depletion region
2. B.Photolithography
3. C.Built-in potential
4. D.Zener versus avalanche breakdown

Answer + AI explanation with Pro

1. A.Depletion region — patterning step exposing photoresist through a mask, with minimum feature size k1·λ/NA, pushed to 13.5 nm EUV for leading-edge nodes
2. B.Depletion region — junction barrier (kT/q)·ln(NA·ND/ni²), about 0.6–0.7 V for silicon, which cannot be measured with an external voltmeter because contact potentials cancel it
3. C.Depletion region — tunnelling in heavily doped junctions below about 5 V with negative temperature coefficient, versus impact ionisation above about 6 V with positive coefficient
4. D.Depletion region — zone on either side of a PN junction emptied of mobile carriers and containing fixed ionised dopants, narrowing under forward bias and widening under reverse bias

Answer + AI explanation with Pro

1. A.gate voltage at which strong inversion begins with surface potential about 2φF, set by oxide thickness, substrate doping and flat-band voltage
2. B.patterning step exposing photoresist through a mask, with minimum feature size k1·λ/NA, pushed to 13.5 nm EUV for leading-edge nodes
3. C.junction barrier (kT/q)·ln(NA·ND/ni²), about 0.6–0.7 V for silicon, which cannot be measured with an external voltmeter because contact potentials cancel it
4. D.drift is carrier motion under an electric field, diffusion is motion from high to low concentration; both are linked through the Einstein relation D/μ = kT/q

Answer + AI explanation with Pro

1. A.Energy band gap
2. B.MOSFET threshold voltage
3. C.Depletion region
4. D.Drift and diffusion currents

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1. A.Drift and diffusion currents — gate voltage at which strong inversion begins with surface potential about 2φF, set by oxide thickness, substrate doping and flat-band voltage
2. B.Drift and diffusion currents — tunnelling in heavily doped junctions below about 5 V with negative temperature coefficient, versus impact ionisation above about 6 V with positive coefficient
3. C.Drift and diffusion currents — zone on either side of a PN junction emptied of mobile carriers and containing fixed ionised dopants, narrowing under forward bias and widening under reverse bias
4. D.Drift and diffusion currents — drift is carrier motion under an electric field, diffusion is motion from high to low concentration; both are linked through the Einstein relation D/μ = kT/q

Answer + AI explanation with Pro

1. A.tunnelling in heavily doped junctions below about 5 V with negative temperature coefficient, versus impact ionisation above about 6 V with positive coefficient
2. B.separation between valence and conduction bands, 1.12 eV for silicon, 0.67 eV for germanium and 1.42 eV for GaAs at room temperature
3. C.drift is carrier motion under an electric field, diffusion is motion from high to low concentration; both are linked through the Einstein relation D/μ = kT/q
4. D.junction barrier (kT/q)·ln(NA·ND/ni²), about 0.6–0.7 V for silicon, which cannot be measured with an external voltmeter because contact potentials cancel it

Answer + AI explanation with Pro

1. A.Intrinsic semiconductor
2. B.Energy band gap
3. C.Depletion region
4. D.Built-in potential

Answer + AI explanation with Pro

1. A.Built-in potential — junction barrier (kT/q)·ln(NA·ND/ni²), about 0.6–0.7 V for silicon, which cannot be measured with an external voltmeter because contact potentials cancel it
2. B.Built-in potential — gate voltage at which strong inversion begins with surface potential about 2φF, set by oxide thickness, substrate doping and flat-band voltage
3. C.Built-in potential — separation between valence and conduction bands, 1.12 eV for silicon, 0.67 eV for germanium and 1.42 eV for GaAs at room temperature
4. D.Built-in potential — patterning step exposing photoresist through a mask, with minimum feature size k1·λ/NA, pushed to 13.5 nm EUV for leading-edge nodes

Answer + AI explanation with Pro

1. A.zone on either side of a PN junction emptied of mobile carriers and containing fixed ionised dopants, narrowing under forward bias and widening under reverse bias
2. B.drift is carrier motion under an electric field, diffusion is motion from high to low concentration; both are linked through the Einstein relation D/μ = kT/q
3. C.gate voltage at which strong inversion begins with surface potential about 2φF, set by oxide thickness, substrate doping and flat-band voltage
4. D.separation between valence and conduction bands, 1.12 eV for silicon, 0.67 eV for germanium and 1.42 eV for GaAs at room temperature

Answer + AI explanation with Pro

1. A.Depletion region
2. B.Energy band gap
3. C.Intrinsic semiconductor
4. D.MOSFET threshold voltage

Answer + AI explanation with Pro

1. A.MOSFET threshold voltage — doping by accelerating ions into the wafer, giving precise dose and depth control at low temperature but requiring an anneal to repair lattice damage, unlike isotropic thermal diffusion
2. B.MOSFET threshold voltage — undoped crystal with equal electron and hole concentrations, about 1.5×10^10 per cm³ for silicon at 300 K, and a Fermi level near mid-gap
3. C.MOSFET threshold voltage — gate voltage at which strong inversion begins with surface potential about 2φF, set by oxide thickness, substrate doping and flat-band voltage
4. D.MOSFET threshold voltage — drift is carrier motion under an electric field, diffusion is motion from high to low concentration; both are linked through the Einstein relation D/μ = kT/q

Answer + AI explanation with Pro

1. A.drift is carrier motion under an electric field, diffusion is motion from high to low concentration; both are linked through the Einstein relation D/μ = kT/q
2. B.separation between valence and conduction bands, 1.12 eV for silicon, 0.67 eV for germanium and 1.42 eV for GaAs at room temperature
3. C.gate voltage at which strong inversion begins with surface potential about 2φF, set by oxide thickness, substrate doping and flat-band voltage
4. D.tunnelling in heavily doped junctions below about 5 V with negative temperature coefficient, versus impact ionisation above about 6 V with positive coefficient

Answer + AI explanation with Pro

1. A.Energy band gap
2. B.Depletion region
3. C.Built-in potential
4. D.Zener versus avalanche breakdown

Answer + AI explanation with Pro

1. A.Zener versus avalanche breakdown — drift is carrier motion under an electric field, diffusion is motion from high to low concentration; both are linked through the Einstein relation D/μ = kT/q
2. B.Zener versus avalanche breakdown — patterning step exposing photoresist through a mask, with minimum feature size k1·λ/NA, pushed to 13.5 nm EUV for leading-edge nodes
3. C.Zener versus avalanche breakdown — doping by accelerating ions into the wafer, giving precise dose and depth control at low temperature but requiring an anneal to repair lattice damage, unlike isotropic thermal diffusion
4. D.Zener versus avalanche breakdown — tunnelling in heavily doped junctions below about 5 V with negative temperature coefficient, versus impact ionisation above about 6 V with positive coefficient

Answer + AI explanation with Pro

1. A.zone on either side of a PN junction emptied of mobile carriers and containing fixed ionised dopants, narrowing under forward bias and widening under reverse bias
2. B.patterning step exposing photoresist through a mask, with minimum feature size k1·λ/NA, pushed to 13.5 nm EUV for leading-edge nodes
3. C.tunnelling in heavily doped junctions below about 5 V with negative temperature coefficient, versus impact ionisation above about 6 V with positive coefficient
4. D.junction barrier (kT/q)·ln(NA·ND/ni²), about 0.6–0.7 V for silicon, which cannot be measured with an external voltmeter because contact potentials cancel it

Answer + AI explanation with Pro

1. A.MOSFET threshold voltage
2. B.Drift and diffusion currents
3. C.Depletion region
4. D.Photolithography

Answer + AI explanation with Pro

1. A.Photolithography — junction barrier (kT/q)·ln(NA·ND/ni²), about 0.6–0.7 V for silicon, which cannot be measured with an external voltmeter because contact potentials cancel it
2. B.Photolithography — patterning step exposing photoresist through a mask, with minimum feature size k1·λ/NA, pushed to 13.5 nm EUV for leading-edge nodes
3. C.Photolithography — zone on either side of a PN junction emptied of mobile carriers and containing fixed ionised dopants, narrowing under forward bias and widening under reverse bias
4. D.Photolithography — doping by accelerating ions into the wafer, giving precise dose and depth control at low temperature but requiring an anneal to repair lattice damage, unlike isotropic thermal diffusion

Answer + AI explanation with Pro

1. A.doping by accelerating ions into the wafer, giving precise dose and depth control at low temperature but requiring an anneal to repair lattice damage, unlike isotropic thermal diffusion
2. B.separation between valence and conduction bands, 1.12 eV for silicon, 0.67 eV for germanium and 1.42 eV for GaAs at room temperature
3. C.drift is carrier motion under an electric field, diffusion is motion from high to low concentration; both are linked through the Einstein relation D/μ = kT/q
4. D.patterning step exposing photoresist through a mask, with minimum feature size k1·λ/NA, pushed to 13.5 nm EUV for leading-edge nodes

Answer + AI explanation with Pro

1. A.Drift and diffusion currents
2. B.Ion implantation
3. C.Built-in potential
4. D.Energy band gap

Answer + AI explanation with Pro

1. A.Ion implantation — tunnelling in heavily doped junctions below about 5 V with negative temperature coefficient, versus impact ionisation above about 6 V with positive coefficient
2. B.Ion implantation — separation between valence and conduction bands, 1.12 eV for silicon, 0.67 eV for germanium and 1.42 eV for GaAs at room temperature
3. C.Ion implantation — patterning step exposing photoresist through a mask, with minimum feature size k1·λ/NA, pushed to 13.5 nm EUV for leading-edge nodes
4. D.Ion implantation — doping by accelerating ions into the wafer, giving precise dose and depth control at low temperature but requiring an anneal to repair lattice damage, unlike isotropic thermal diffusion

Answer + AI explanation with Pro