Qualcomm

Core · core branches incl. ECE, EE· Updated 25 Sep 2026

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Qualcomm India hires freshers mainly through campus drives, often as a 6-month internship leading to a full-time offer: a 90-minute online test with aptitude, C programming and digital-electronics sections and negative marking, then two technical interviews and a short HR round. Hardware roles want ECE/EE graduates with VLSI or embedded skills.

Engineer (VLSI, Embedded, Software)

Electronics & Comm. practice questions on placd

Who can apply

Bachelor's degree in electrical/electronics, computer science or a related field for Engineer (hardware) campus hires; VLSI, embedded and ECE backgrounds preferred
No single published CGPA cutoff found; one NIT Durgapur full-time form asked for 7.5 CGPA and 75% in 10th and 12th (reported)
Skills listed for hardware campus hires: Verilog or VHDL, C/C++ and Tcl/Perl/shell scripting

Key facts

Test selectivity, one campus (reported): About 1,500 took the online test; about 35 reached interviews [source]
Negative marking (reported): +1 for a correct answer, -0.25 for a wrong one [source]
Internship stipend (NIT Durgapur form): ₹45,000 per month for a 6-month internship in Hyderabad (reported) [source]
Hardware campus-hire domains: SoC physical design, SoC validation, digital ASIC design, design/SoC verification, CPU design, RF and analog layout [source]

Interview process

1Online test90 minutes: three 20-question sections of 30 minutes each – aptitude, C programming, and digital electronics (or CS); +1/-0.25 marking reported.

2Technical interview 1CMOS inverter, noise margins, MOSFET basics, FSMs and a Verilog counter; verification roles add C coding such as merge sort.

3Technical interview 2Setup/hold and STA, clock skew and jitter, synchronizers, caches and SRAM vs DRAM, gate-level puzzles, plus a project discussion.

4HR roundShort round on background, strengths, motivation for Qualcomm and location preference.

Questions to expect in Qualcomm interviews

Drawn from reported fresher tests and interviews (sources below), with short answers. Practise more on placd.

CMOS / VLSI

Draw the CMOS inverter transfer characteristic. What are its switching threshold and noise margins?

The switching threshold VM is where Vin = Vout; both transistors are saturated there and the curve is steepest. With the PMOS sized about 2–3 times wider than the NMOS to offset lower hole mobility, VM is near VDD/2. VIL and VIH are the points where the slope is -1. Noise margins: NMH = VOH - VIH and NML = VIL - VOL.

Digital design

Implement an OR gate using NAND gates.

By De Morgan, A + B = NOT(NOT A AND NOT B). Make NOT A and NOT B with two NAND gates whose inputs are tied together (NAND(A,A) and NAND(B,B)), then feed both into a third NAND gate. The output is A OR B, using three NAND gates.

Verilog

Write Verilog for a mod-3 counter. What mistakes are common?

always @(posedge clk or posedge rst) if (rst) q <= 2'd0; else if (q == 2'd2) q <= 2'd0; else q <= q + 1'b1; with q declared as reg [1:0]. Common mistakes: using blocking (=) instead of non-blocking (<=) assignments in sequential logic, leaving out the reset, and not wrapping at 2, so the counter wrongly reaches 3.

Static timing

What are setup time and hold time?

Setup time is the minimum time data must be stable before the active clock edge; hold time is the minimum time it must stay stable after the edge. Setup check: Tclk-q + Tlogic(max) + Tsetup <= Tclock period + skew. Hold check: Tclk-q + Tlogic(min) >= Thold + skew (skew = capture minus launch clock delay). Fix setup by cutting logic or lowering frequency; fix hold by adding delay.

Clock domain crossing

Why do we use a 2-flip-flop synchronizer?

A signal from an asynchronous clock domain can violate setup or hold at the first flop and make it metastable. The second flop gives the first a full clock cycle to settle before its output is used, and mean time between failures grows exponentially with that settling time. It suits single-bit control signals; multi-bit buses need Gray code, handshakes or an asynchronous FIFO.

Memory

What is the difference between SRAM and DRAM?

SRAM stores a bit in a 6-transistor cell of cross-coupled inverters: no refresh, fast, but large, so it is used for caches and registers. DRAM stores a bit as charge on a capacitor with one access transistor (1T1C): dense and cheap, but the charge leaks, so it needs periodic refresh and reads are destructive; it is used for main memory. Both are volatile.

About Qualcomm hiring

What is the CGPA cutoff for Qualcomm?

We found no single published Qualcomm cutoff. One NIT Durgapur full-time form asked for 7.5 CGPA and 75% in 10th and 12th. Clearing the cutoff only gets you to the online test, which is the real filter.

Does the Qualcomm online test have negative marking?

Reported on-campus tests had three 30-minute sections (aptitude, C programming, digital electronics) of 20 questions each, marked +1 for a correct answer and -0.25 for a wrong one. Guess only when you can rule out options.

What should ECE students revise for Qualcomm hardware interviews?

CMOS inverter and noise margins, MOSFET basics, FSM design and Verilog, setup/hold time and STA, clock skew and synchronizers, and memory (SRAM vs DRAM, caches). Expect to write small Verilog or C code during the interview.

Sources

Checked on 25 Sep 2026. Recruitment rules change each cycle — confirm dates and eligibility in the official notification.