Texas Instruments

Q: What is the Texas Instruments online test pattern for freshers in India?

It varies by drive. Reports describe an aptitude section plus one or two profile sections (analog, digital or embedded), often about 20 questions each. One 2023 campus drive had 70 questions in 2 hours 15 minutes with 0.25 negative marking. The test is the main filter before interviews.

Q: What salary does Texas Instruments pay freshers in India?

Levels.fyi reports about ₹24–26 lakh total compensation at TI's entry level in India (level 24, 0–1 years). CET Trivandrum reported a ₹38.5 LPA CTC for its 2024-25 TI offers. Figures vary by college and role, so treat them as reported, not official.

Q: Which branches can apply to Texas Instruments India?

ECE, EEE and Electronics and Instrumentation students at B.Tech or M.Tech level, with 60% (or 7.0 CGPA) and no active backlogs, as reported. Analog, digital and embedded profiles each have their own test section and interview questions.

Core · core branches incl. ECE, EE· Updated 25 Sep 2026

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Texas Instruments hires ECE and EEE freshers in India mainly through campus drives: an online test with aptitude plus an analog, digital or embedded section, one to three technical interviews that open with your project, then an HR round. The test pattern and number of interviews vary by drive.

Analog / Digital / Embedded Engineer

Electronics & Comm. practice questions on placd

Who can apply

B.Tech or M.Tech in ECE, EEE or Electronics and Instrumentation
60% in Class 10, Class 12 and graduation, or 7.0 CGPA (reported)
No active backlogs when you apply

Key facts

Entry-level pay (India, hardware): About ₹26 LPA total comp at level 24, 0–1 years (reported) [source]
Entry-level pay (India, analog engineer): About ₹24 LPA total comp at level 24 (reported) [source]
Campus CTC, one college: ₹38.5 LPA for TI offers in CET Trivandrum ECE, 2024-25 placements (reported) [source]
2023 digital/analog online test: 20 analog + 20 digital + 30 cognitive questions, 2 h 15 min, +1/-0.25 (reported) [source]
Interview opening: 20-30 minutes on one CV project before core questions (reported) [source]

Interview process

1Online testAptitude plus one or two profile sections (analog, digital or embedded), often about 20 questions each. One 2023 drive: 70 questions in 2 h 15 min, -0.25 marking.

2Technical interview 1Starts with your CV: 20-30 minutes on one project, then core questions for your chosen profile.

3Technical interview 2 (some drives)Deeper profile questions. Analog: RC transients, op-amps, MOSFET regions. Digital: FSMs, setup/hold, Verilog. Embedded: C, memory, caches.

4HR interviewMotivation, career goals and why TI.

Questions to expect in Texas Instruments interviews

Drawn from reported fresher tests and interviews (sources below), with short answers. Practise more on placd.

Analog circuits

A step voltage V is applied to a series RC circuit. How does the capacitor voltage behave?

It rises exponentially: Vc(t) = V(1 - e^(-t/RC)). The time constant tau = RC; after one tau Vc is about 63% of V, and after about 5 tau it is treated as fully charged (over 99%). The current jumps to V/R at t = 0 and decays as (V/R)e^(-t/RC).

Op-amps

What is virtual ground in an inverting amplifier, and what is its gain?

With negative feedback and very high open-loop gain, the op-amp keeps its two inputs at nearly the same voltage. The non-inverting input is grounded, so the inverting node sits at about 0 V without being connected to ground: a virtual ground. No current enters the op-amp, so Vin/Rin flows through Rf, giving Vout/Vin = -Rf/Rin.

MOSFET

What are the operating regions of an NMOS transistor?

Cutoff: VGS < Vth, almost no drain current. Linear (triode): VGS > Vth and VDS < VGS - Vth; it acts like a voltage-controlled resistor, ID = k[(VGS - Vth)VDS - VDS^2/2]. Saturation: VGS > Vth and VDS >= VGS - Vth; ID = (k/2)(VGS - Vth)^2, nearly independent of VDS. Here k = un Cox W/L.

Static timing

Given clock-to-Q delay, combinational delay and setup/hold times, what is the minimum clock period and the hold condition?

With skew = capture clock arrival minus launch clock arrival: setup needs Tclk >= Tcq + Tcomb(max) + Tsetup - skew; hold needs Tcq + Tcomb(min) >= Thold + skew. The hold check does not contain the clock period, so a hold violation cannot be fixed by slowing the clock; you add delay in the data path instead.

Verilog

What is the difference between blocking and non-blocking assignments?

Blocking (=) executes in order, so the next statement sees the new value. Non-blocking (<=) evaluates all right-hand sides first and updates at the end of the time step. Use <= in clocked always blocks, so a <= b; b <= a; swaps like real flip-flops, and = for combinational logic.

C / embedded

How do you check in C whether a machine is little-endian or big-endian?

Store a multi-byte integer and read the byte at its lowest address: unsigned int x = 1; char *p = (char *)&x; If *p == 1, the least significant byte is stored first, so the machine is little-endian; otherwise it is big-endian. x86 processors are little-endian.

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What is the Texas Instruments online test pattern for freshers in India?