Analog & Mixed-Signal Design interview questions

1. A.differential input stage followed by a common-source gain stage, Miller compensated with a capacitor across the second stage to place the dominant pole
2. B.linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
3. C.random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
4. D.cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock

Answer + AI explanation with Pro

1. A.Guard rings and dummy devices
2. B.Two-stage op-amp
3. C.Bandgap reference
4. D.Sigma-delta ADC

Answer + AI explanation with Pro

1. A.Two-stage op-amp — differential input stage followed by a common-source gain stage, Miller compensated with a capacitor across the second stage to place the dominant pole
2. B.Two-stage op-amp — circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
3. C.Two-stage op-amp — Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
4. D.Two-stage op-amp — linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat

Answer + AI explanation with Pro

1. A.feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
2. B.substrate-tied rings around sensitive blocks isolate noise, and dummy fingers at array edges equalise etch and stress so edge transistors match interior ones
3. C.oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
4. D.circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature

Answer + AI explanation with Pro

1. A.Two-stage op-amp
2. B.Guard rings and dummy devices
3. C.Bandgap reference
4. D.Sigma-delta ADC

Answer + AI explanation with Pro

1. A.Bandgap reference — linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
2. B.Bandgap reference — feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
3. C.Bandgap reference — Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
4. D.Bandgap reference — circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature

Answer + AI explanation with Pro

1. A.oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
2. B.differential input stage followed by a common-source gain stage, Miller compensated with a capacitor across the second stage to place the dominant pole
3. C.random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
4. D.linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat

Answer + AI explanation with Pro

1. A.Low-dropout regulator
2. B.Device matching
3. C.Pipelined ADC
4. D.Virtuoso

Answer + AI explanation with Pro

1. A.Low-dropout regulator — random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
2. B.Low-dropout regulator — cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock
3. C.Low-dropout regulator — Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
4. D.Low-dropout regulator — linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat

Answer + AI explanation with Pro

1. A.oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
2. B.random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
3. C.cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock
4. D.feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling

Answer + AI explanation with Pro

1. A.Bandgap reference
2. B.Sigma-delta ADC
3. C.Low-dropout regulator
4. D.Phase-locked loop

Answer + AI explanation with Pro

1. A.Phase-locked loop — oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
2. B.Phase-locked loop — Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
3. C.Phase-locked loop — linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
4. D.Phase-locked loop — feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling

Answer + AI explanation with Pro

1. A.Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
2. B.circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
3. C.feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
4. D.cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock

Answer + AI explanation with Pro

1. A.Two-stage op-amp
2. B.Bandgap reference
3. C.Low-dropout regulator
4. D.Pipelined ADC

Answer + AI explanation with Pro

1. A.Pipelined ADC — cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock
2. B.Pipelined ADC — oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
3. C.Pipelined ADC — circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
4. D.Pipelined ADC — random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation

Answer + AI explanation with Pro

1. A.linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
2. B.feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
3. C.oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
4. D.circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature

Answer + AI explanation with Pro

1. A.Low-dropout regulator
2. B.Bandgap reference
3. C.Two-stage op-amp
4. D.Sigma-delta ADC

Answer + AI explanation with Pro

1. A.Sigma-delta ADC — substrate-tied rings around sensitive blocks isolate noise, and dummy fingers at array edges equalise etch and stress so edge transistors match interior ones
2. B.Sigma-delta ADC — differential input stage followed by a common-source gain stage, Miller compensated with a capacitor across the second stage to place the dominant pole
3. C.Sigma-delta ADC — oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
4. D.Sigma-delta ADC — feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling

Answer + AI explanation with Pro

1. A.feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
2. B.circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
3. C.oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
4. D.Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification

Answer + AI explanation with Pro

1. A.Bandgap reference
2. B.Low-dropout regulator
3. C.Pipelined ADC
4. D.Virtuoso

Answer + AI explanation with Pro

1. A.Virtuoso — feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
2. B.Virtuoso — random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
3. C.Virtuoso — substrate-tied rings around sensitive blocks isolate noise, and dummy fingers at array edges equalise etch and stress so edge transistors match interior ones
4. D.Virtuoso — Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification

Answer + AI explanation with Pro

1. A.linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
2. B.random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
3. C.Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
4. D.cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock

Answer + AI explanation with Pro

1. A.Sigma-delta ADC
2. B.Phase-locked loop
3. C.Low-dropout regulator
4. D.Device matching

Answer + AI explanation with Pro

1. A.Device matching — cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock
2. B.Device matching — random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
3. C.Device matching — linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
4. D.Device matching — substrate-tied rings around sensitive blocks isolate noise, and dummy fingers at array edges equalise etch and stress so edge transistors match interior ones

Answer + AI explanation with Pro

1. A.substrate-tied rings around sensitive blocks isolate noise, and dummy fingers at array edges equalise etch and stress so edge transistors match interior ones
2. B.circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
3. C.feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
4. D.random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation

Answer + AI explanation with Pro

1. A.Phase-locked loop
2. B.Guard rings and dummy devices
3. C.Pipelined ADC
4. D.Bandgap reference

Answer + AI explanation with Pro

1. A.Guard rings and dummy devices — Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
2. B.Guard rings and dummy devices — circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
3. C.Guard rings and dummy devices — random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
4. D.Guard rings and dummy devices — substrate-tied rings around sensitive blocks isolate noise, and dummy fingers at array edges equalise etch and stress so edge transistors match interior ones

Answer + AI explanation with Pro