Physical Design interview questions

1. A.creation of rings and straps in upper metals plus standard-cell rails so every instance sees supply within the IR-drop budget, usually a few percent of VDD
2. B.Cadence place-and-route platform with GigaPlace and GigaOpt engines that shares its timer with Tempus so implementation correlates with signoff
3. C.first layout step fixing die size, core utilisation of typically 60–70%, macro placement, pin assignment and blockages, which largely decides routability
4. D.supply voltage loss along the power grid, static from average current and dynamic from switching peaks, checked with RedHawk or Voltus before signoff

Answer + AI explanation with Pro

1. A.Floorplanning
2. B.Congestion
3. C.Clock tree synthesis
4. D.Innovus

Answer + AI explanation with Pro

1. A.Floorplanning — supply voltage loss along the power grid, static from average current and dynamic from switching peaks, checked with RedHawk or Voltus before signoff
2. B.Floorplanning — building a buffered clock distribution to every flop with minimal skew and insertion delay, using H-trees or meshes and useful-skew adjustments
3. C.Floorplanning — first layout step fixing die size, core utilisation of typically 60–70%, macro placement, pin assignment and blockages, which largely decides routability
4. D.Floorplanning — legal non-overlapping positioning of standard cells on rows to minimise wirelength and meet timing, followed by legalisation and congestion-aware refinement

Answer + AI explanation with Pro

1. A.creation of rings and straps in upper metals plus standard-cell rails so every instance sees supply within the IR-drop budget, usually a few percent of VDD
2. B.gradual transport of metal atoms under high current density that voids or shorts wires, bounded by width-dependent current limits from the foundry and worsened by temperature
3. C.demand for routing tracks exceeding supply in a region, shown as overflow maps and fixed by spreading cells, adding blockages or moving macros
4. D.supply voltage loss along the power grid, static from average current and dynamic from switching peaks, checked with RedHawk or Voltus before signoff

Answer + AI explanation with Pro

1. A.Innovus
2. B.Signoff DRC and LVS
3. C.Clock tree synthesis
4. D.Power planning

Answer + AI explanation with Pro

1. A.Power planning — creation of rings and straps in upper metals plus standard-cell rails so every instance sees supply within the IR-drop budget, usually a few percent of VDD
2. B.Power planning — final physical verification with Calibre: design-rule check against the foundry deck and layout-versus-schematic proving the GDS matches the netlist
3. C.Power planning — first layout step fixing die size, core utilisation of typically 60–70%, macro placement, pin assignment and blockages, which largely decides routability
4. D.Power planning — demand for routing tracks exceeding supply in a region, shown as overflow maps and fixed by spreading cells, adding blockages or moving macros

Answer + AI explanation with Pro

1. A.creation of rings and straps in upper metals plus standard-cell rails so every instance sees supply within the IR-drop budget, usually a few percent of VDD
2. B.first layout step fixing die size, core utilisation of typically 60–70%, macro placement, pin assignment and blockages, which largely decides routability
3. C.legal non-overlapping positioning of standard cells on rows to minimise wirelength and meet timing, followed by legalisation and congestion-aware refinement
4. D.supply voltage loss along the power grid, static from average current and dynamic from switching peaks, checked with RedHawk or Voltus before signoff

Answer + AI explanation with Pro

1. A.Clock tree synthesis
2. B.Placement
3. C.Congestion
4. D.IR drop

Answer + AI explanation with Pro

1. A.Placement — supply voltage loss along the power grid, static from average current and dynamic from switching peaks, checked with RedHawk or Voltus before signoff
2. B.Placement — gradual transport of metal atoms under high current density that voids or shorts wires, bounded by width-dependent current limits from the foundry and worsened by temperature
3. C.Placement — legal non-overlapping positioning of standard cells on rows to minimise wirelength and meet timing, followed by legalisation and congestion-aware refinement
4. D.Placement — building a buffered clock distribution to every flop with minimal skew and insertion delay, using H-trees or meshes and useful-skew adjustments

Answer + AI explanation with Pro

1. A.supply voltage loss along the power grid, static from average current and dynamic from switching peaks, checked with RedHawk or Voltus before signoff
2. B.first layout step fixing die size, core utilisation of typically 60–70%, macro placement, pin assignment and blockages, which largely decides routability
3. C.legal non-overlapping positioning of standard cells on rows to minimise wirelength and meet timing, followed by legalisation and congestion-aware refinement
4. D.building a buffered clock distribution to every flop with minimal skew and insertion delay, using H-trees or meshes and useful-skew adjustments

Answer + AI explanation with Pro

1. A.Clock tree synthesis
2. B.IR drop
3. C.Electromigration
4. D.Innovus

Answer + AI explanation with Pro

1. A.Clock tree synthesis — building a buffered clock distribution to every flop with minimal skew and insertion delay, using H-trees or meshes and useful-skew adjustments
2. B.Clock tree synthesis — first layout step fixing die size, core utilisation of typically 60–70%, macro placement, pin assignment and blockages, which largely decides routability
3. C.Clock tree synthesis — legal non-overlapping positioning of standard cells on rows to minimise wirelength and meet timing, followed by legalisation and congestion-aware refinement
4. D.Clock tree synthesis — Cadence place-and-route platform with GigaPlace and GigaOpt engines that shares its timer with Tempus so implementation correlates with signoff

Answer + AI explanation with Pro

1. A.first layout step fixing die size, core utilisation of typically 60–70%, macro placement, pin assignment and blockages, which largely decides routability
2. B.Cadence place-and-route platform with GigaPlace and GigaOpt engines that shares its timer with Tempus so implementation correlates with signoff
3. C.demand for routing tracks exceeding supply in a region, shown as overflow maps and fixed by spreading cells, adding blockages or moving macros
4. D.legal non-overlapping positioning of standard cells on rows to minimise wirelength and meet timing, followed by legalisation and congestion-aware refinement

Answer + AI explanation with Pro

1. A.Congestion
2. B.Floorplanning
3. C.Placement
4. D.Innovus

Answer + AI explanation with Pro

1. A.Congestion — gradual transport of metal atoms under high current density that voids or shorts wires, bounded by width-dependent current limits from the foundry and worsened by temperature
2. B.Congestion — first layout step fixing die size, core utilisation of typically 60–70%, macro placement, pin assignment and blockages, which largely decides routability
3. C.Congestion — supply voltage loss along the power grid, static from average current and dynamic from switching peaks, checked with RedHawk or Voltus before signoff
4. D.Congestion — demand for routing tracks exceeding supply in a region, shown as overflow maps and fixed by spreading cells, adding blockages or moving macros

Answer + AI explanation with Pro

1. A.legal non-overlapping positioning of standard cells on rows to minimise wirelength and meet timing, followed by legalisation and congestion-aware refinement
2. B.supply voltage loss along the power grid, static from average current and dynamic from switching peaks, checked with RedHawk or Voltus before signoff
3. C.first layout step fixing die size, core utilisation of typically 60–70%, macro placement, pin assignment and blockages, which largely decides routability
4. D.building a buffered clock distribution to every flop with minimal skew and insertion delay, using H-trees or meshes and useful-skew adjustments

Answer + AI explanation with Pro

1. A.Power planning
2. B.IR drop
3. C.Signoff DRC and LVS
4. D.Placement

Answer + AI explanation with Pro

1. A.IR drop — supply voltage loss along the power grid, static from average current and dynamic from switching peaks, checked with RedHawk or Voltus before signoff
2. B.IR drop — first layout step fixing die size, core utilisation of typically 60–70%, macro placement, pin assignment and blockages, which largely decides routability
3. C.IR drop — demand for routing tracks exceeding supply in a region, shown as overflow maps and fixed by spreading cells, adding blockages or moving macros
4. D.IR drop — Cadence place-and-route platform with GigaPlace and GigaOpt engines that shares its timer with Tempus so implementation correlates with signoff

Answer + AI explanation with Pro

1. A.supply voltage loss along the power grid, static from average current and dynamic from switching peaks, checked with RedHawk or Voltus before signoff
2. B.gradual transport of metal atoms under high current density that voids or shorts wires, bounded by width-dependent current limits from the foundry and worsened by temperature
3. C.legal non-overlapping positioning of standard cells on rows to minimise wirelength and meet timing, followed by legalisation and congestion-aware refinement
4. D.Cadence place-and-route platform with GigaPlace and GigaOpt engines that shares its timer with Tempus so implementation correlates with signoff

Answer + AI explanation with Pro

1. A.Signoff DRC and LVS
2. B.Power planning
3. C.Congestion
4. D.Electromigration

Answer + AI explanation with Pro

1. A.Electromigration — creation of rings and straps in upper metals plus standard-cell rails so every instance sees supply within the IR-drop budget, usually a few percent of VDD
2. B.Electromigration — building a buffered clock distribution to every flop with minimal skew and insertion delay, using H-trees or meshes and useful-skew adjustments
3. C.Electromigration — gradual transport of metal atoms under high current density that voids or shorts wires, bounded by width-dependent current limits from the foundry and worsened by temperature
4. D.Electromigration — demand for routing tracks exceeding supply in a region, shown as overflow maps and fixed by spreading cells, adding blockages or moving macros

Answer + AI explanation with Pro

1. A.building a buffered clock distribution to every flop with minimal skew and insertion delay, using H-trees or meshes and useful-skew adjustments
2. B.Cadence place-and-route platform with GigaPlace and GigaOpt engines that shares its timer with Tempus so implementation correlates with signoff
3. C.creation of rings and straps in upper metals plus standard-cell rails so every instance sees supply within the IR-drop budget, usually a few percent of VDD
4. D.gradual transport of metal atoms under high current density that voids or shorts wires, bounded by width-dependent current limits from the foundry and worsened by temperature

Answer + AI explanation with Pro

1. A.Floorplanning
2. B.Innovus
3. C.Electromigration
4. D.Clock tree synthesis

Answer + AI explanation with Pro

1. A.Innovus — Cadence place-and-route platform with GigaPlace and GigaOpt engines that shares its timer with Tempus so implementation correlates with signoff
2. B.Innovus — final physical verification with Calibre: design-rule check against the foundry deck and layout-versus-schematic proving the GDS matches the netlist
3. C.Innovus — first layout step fixing die size, core utilisation of typically 60–70%, macro placement, pin assignment and blockages, which largely decides routability
4. D.Innovus — demand for routing tracks exceeding supply in a region, shown as overflow maps and fixed by spreading cells, adding blockages or moving macros

Answer + AI explanation with Pro

1. A.gradual transport of metal atoms under high current density that voids or shorts wires, bounded by width-dependent current limits from the foundry and worsened by temperature
2. B.supply voltage loss along the power grid, static from average current and dynamic from switching peaks, checked with RedHawk or Voltus before signoff
3. C.Cadence place-and-route platform with GigaPlace and GigaOpt engines that shares its timer with Tempus so implementation correlates with signoff
4. D.final physical verification with Calibre: design-rule check against the foundry deck and layout-versus-schematic proving the GDS matches the netlist

Answer + AI explanation with Pro

1. A.Placement
2. B.Signoff DRC and LVS
3. C.Electromigration
4. D.Power planning

Answer + AI explanation with Pro

1. A.Signoff DRC and LVS — final physical verification with Calibre: design-rule check against the foundry deck and layout-versus-schematic proving the GDS matches the netlist
2. B.Signoff DRC and LVS — building a buffered clock distribution to every flop with minimal skew and insertion delay, using H-trees or meshes and useful-skew adjustments
3. C.Signoff DRC and LVS — demand for routing tracks exceeding supply in a region, shown as overflow maps and fixed by spreading cells, adding blockages or moving macros
4. D.Signoff DRC and LVS — gradual transport of metal atoms under high current density that voids or shorts wires, bounded by width-dependent current limits from the foundry and worsened by temperature

Answer + AI explanation with Pro