27 Synthesis & Logic Optimization questions from the VLSI Design bank, written for Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd.
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A.Cadence synthesis tool whose physically aware mode shares engines with Innovus so netlists are optimised against real floorplan wire loads
B.translation of RTL into a gate-level netlist of standard cells under timing, area and power constraints, with technology mapping to the target library
C.Synopsys Design Constraints: create_clock, set_input_delay, set_output_delay and timing exceptions that define intent shared by synthesis, place-and-route and STA
D.moving registers across combinational logic without changing function so stage delays balance, raising the achievable frequency of a pipeline
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2. Which term means: "translation of RTL into a gate-level netlist of standard cells under timing, area and power constraints, with technology mapping to the target library"?
Junior
A.Logic synthesis
B.Non-synthesisable constructs
C.Timing-driven synthesis
D.Equivalence checking
Answer + AI explanation with Pro
3. Which statement is correct?
Junior
A.Logic synthesis — formal proof that RTL and netlist, or two netlists, implement the same function using Formality or Conformal, catching synthesis or ECO errors without simulation
B.Logic synthesis — initial blocks, # delays, $display, fork-join and real arithmetic are ignored or rejected by synthesis, so RTL that simulates correctly may still not build
C.Logic synthesis — synthesis optimisation letting mutually exclusive operations use one arithmetic unit through multiplexing, saving area at the cost of mux delay on the shared path
D.Logic synthesis — translation of RTL into a gate-level netlist of standard cells under timing, area and power constraints, with technology mapping to the target library
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4. What is SDC constraints?
Junior
A.Synopsys Design Constraints: create_clock, set_input_delay, set_output_delay and timing exceptions that define intent shared by synthesis, place-and-route and STA
B.synthesis optimisation letting mutually exclusive operations use one arithmetic unit through multiplexing, saving area at the cost of mux delay on the shared path
C.moving registers across combinational logic without changing function so stage delays balance, raising the achievable frequency of a pipeline
D.formal proof that RTL and netlist, or two netlists, implement the same function using Formality or Conformal, catching synthesis or ECO errors without simulation
Answer + AI explanation with Pro
5. Which term means: "Synopsys Design Constraints: create_clock, set_input_delay, set_output_delay and timing exceptions that define intent shared by synthesis, place-and-route and STA"?
B.SDC constraints — formal proof that RTL and netlist, or two netlists, implement the same function using Formality or Conformal, catching synthesis or ECO errors without simulation
C.SDC constraints — Synopsys Design Constraints: create_clock, set_input_delay, set_output_delay and timing exceptions that define intent shared by synthesis, place-and-route and STA
D.SDC constraints — translation of RTL into a gate-level netlist of standard cells under timing, area and power constraints, with technology mapping to the target library
Answer + AI explanation with Pro
7. What is Non-synthesisable constructs?
Junior
A.initial blocks, # delays, $display, fork-join and real arithmetic are ignored or rejected by synthesis, so RTL that simulates correctly may still not build
B.formal proof that RTL and netlist, or two netlists, implement the same function using Formality or Conformal, catching synthesis or ECO errors without simulation
C.Cadence synthesis tool whose physically aware mode shares engines with Innovus so netlists are optimised against real floorplan wire loads
D.translation of RTL into a gate-level netlist of standard cells under timing, area and power constraints, with technology mapping to the target library
Answer + AI explanation with Pro
8. Which term means: "initial blocks, # delays, $display, fork-join and real arithmetic are ignored or rejected by synthesis, so RTL that simulates correctly may still not build"?
Junior
A.Genus
B.Non-synthesisable constructs
C.Retiming
D.Equivalence checking
Answer + AI explanation with Pro
9. Which statement is correct?
Junior
A.Non-synthesisable constructs — moving registers across combinational logic without changing function so stage delays balance, raising the achievable frequency of a pipeline
B.Non-synthesisable constructs — Synopsys Design Constraints: create_clock, set_input_delay, set_output_delay and timing exceptions that define intent shared by synthesis, place-and-route and STA
C.Non-synthesisable constructs — optimisation that focuses on critical paths, applying upsizing, buffering, logic restructuring and duplication to meet the clock while leaving non-critical logic small
D.Non-synthesisable constructs — initial blocks, # delays, $display, fork-join and real arithmetic are ignored or rejected by synthesis, so RTL that simulates correctly may still not build
Answer + AI explanation with Pro
10. What is Design Compiler?
Mid
A.Synopsys Design Constraints: create_clock, set_input_delay, set_output_delay and timing exceptions that define intent shared by synthesis, place-and-route and STA
B.Synopsys RTL synthesis tool whose topographical mode uses placement-aware wire estimates so post-synthesis timing correlates with physical design
C.moving registers across combinational logic without changing function so stage delays balance, raising the achievable frequency of a pipeline
D.synthesis optimisation letting mutually exclusive operations use one arithmetic unit through multiplexing, saving area at the cost of mux delay on the shared path
Answer + AI explanation with Pro
11. Which term means: "Synopsys RTL synthesis tool whose topographical mode uses placement-aware wire estimates so post-synthesis timing correlates with physical design"?
Mid
A.Logic synthesis
B.Non-synthesisable constructs
C.Timing-driven synthesis
D.Design Compiler
Answer + AI explanation with Pro
12. Which statement is correct?
Mid
A.Design Compiler — optimisation that focuses on critical paths, applying upsizing, buffering, logic restructuring and duplication to meet the clock while leaving non-critical logic small
B.Design Compiler — Cadence synthesis tool whose physically aware mode shares engines with Innovus so netlists are optimised against real floorplan wire loads
C.Design Compiler — Synopsys Design Constraints: create_clock, set_input_delay, set_output_delay and timing exceptions that define intent shared by synthesis, place-and-route and STA
A.translation of RTL into a gate-level netlist of standard cells under timing, area and power constraints, with technology mapping to the target library
B.synthesis optimisation letting mutually exclusive operations use one arithmetic unit through multiplexing, saving area at the cost of mux delay on the shared path
C.Synopsys Design Constraints: create_clock, set_input_delay, set_output_delay and timing exceptions that define intent shared by synthesis, place-and-route and STA
D.Cadence synthesis tool whose physically aware mode shares engines with Innovus so netlists are optimised against real floorplan wire loads
Answer + AI explanation with Pro
14. Which term means: "Cadence synthesis tool whose physically aware mode shares engines with Innovus so netlists are optimised against real floorplan wire loads"?
Mid
A.Genus
B.Equivalence checking
C.Resource sharing
D.Non-synthesisable constructs
Answer + AI explanation with Pro
15. Which statement is correct?
Mid
A.Genus — Synopsys RTL synthesis tool whose topographical mode uses placement-aware wire estimates so post-synthesis timing correlates with physical design
B.Genus — moving registers across combinational logic without changing function so stage delays balance, raising the achievable frequency of a pipeline
C.Genus — optimisation that focuses on critical paths, applying upsizing, buffering, logic restructuring and duplication to meet the clock while leaving non-critical logic small
D.Genus — Cadence synthesis tool whose physically aware mode shares engines with Innovus so netlists are optimised against real floorplan wire loads
Answer + AI explanation with Pro
16. What is Timing-driven synthesis?
Mid
A.Synopsys Design Constraints: create_clock, set_input_delay, set_output_delay and timing exceptions that define intent shared by synthesis, place-and-route and STA
B.Synopsys RTL synthesis tool whose topographical mode uses placement-aware wire estimates so post-synthesis timing correlates with physical design
C.moving registers across combinational logic without changing function so stage delays balance, raising the achievable frequency of a pipeline
D.optimisation that focuses on critical paths, applying upsizing, buffering, logic restructuring and duplication to meet the clock while leaving non-critical logic small
Answer + AI explanation with Pro
17. Which term means: "optimisation that focuses on critical paths, applying upsizing, buffering, logic restructuring and duplication to meet the clock while leaving non-critical logic small"?
Mid
A.Equivalence checking
B.Retiming
C.Design Compiler
D.Timing-driven synthesis
Answer + AI explanation with Pro
18. Which statement is correct?
Mid
A.Timing-driven synthesis — moving registers across combinational logic without changing function so stage delays balance, raising the achievable frequency of a pipeline
C.Timing-driven synthesis — initial blocks, # delays, $display, fork-join and real arithmetic are ignored or rejected by synthesis, so RTL that simulates correctly may still not build
D.Timing-driven synthesis — optimisation that focuses on critical paths, applying upsizing, buffering, logic restructuring and duplication to meet the clock while leaving non-critical logic small
Answer + AI explanation with Pro
19. What is Retiming?
Mid
A.Synopsys Design Constraints: create_clock, set_input_delay, set_output_delay and timing exceptions that define intent shared by synthesis, place-and-route and STA
B.moving registers across combinational logic without changing function so stage delays balance, raising the achievable frequency of a pipeline
C.synthesis optimisation letting mutually exclusive operations use one arithmetic unit through multiplexing, saving area at the cost of mux delay on the shared path
D.Cadence synthesis tool whose physically aware mode shares engines with Innovus so netlists are optimised against real floorplan wire loads
Answer + AI explanation with Pro
20. Which term means: "moving registers across combinational logic without changing function so stage delays balance, raising the achievable frequency of a pipeline"?
Mid
A.Retiming
B.Logic synthesis
C.Non-synthesisable constructs
D.Resource sharing
Answer + AI explanation with Pro
21. Which statement is correct?
Mid
A.Retiming — Cadence synthesis tool whose physically aware mode shares engines with Innovus so netlists are optimised against real floorplan wire loads
B.Retiming — translation of RTL into a gate-level netlist of standard cells under timing, area and power constraints, with technology mapping to the target library
C.Retiming — moving registers across combinational logic without changing function so stage delays balance, raising the achievable frequency of a pipeline
D.Retiming — formal proof that RTL and netlist, or two netlists, implement the same function using Formality or Conformal, catching synthesis or ECO errors without simulation
Answer + AI explanation with Pro
22. What is Equivalence checking?
Senior
A.formal proof that RTL and netlist, or two netlists, implement the same function using Formality or Conformal, catching synthesis or ECO errors without simulation
B.Synopsys RTL synthesis tool whose topographical mode uses placement-aware wire estimates so post-synthesis timing correlates with physical design
C.optimisation that focuses on critical paths, applying upsizing, buffering, logic restructuring and duplication to meet the clock while leaving non-critical logic small
D.moving registers across combinational logic without changing function so stage delays balance, raising the achievable frequency of a pipeline
Answer + AI explanation with Pro
23. Which term means: "formal proof that RTL and netlist, or two netlists, implement the same function using Formality or Conformal, catching synthesis or ECO errors without simulation"?
Senior
A.Resource sharing
B.Timing-driven synthesis
C.Genus
D.Equivalence checking
Answer + AI explanation with Pro
24. Which statement is correct?
Senior
A.Equivalence checking — Synopsys Design Constraints: create_clock, set_input_delay, set_output_delay and timing exceptions that define intent shared by synthesis, place-and-route and STA
B.Equivalence checking — synthesis optimisation letting mutually exclusive operations use one arithmetic unit through multiplexing, saving area at the cost of mux delay on the shared path
C.Equivalence checking — formal proof that RTL and netlist, or two netlists, implement the same function using Formality or Conformal, catching synthesis or ECO errors without simulation
A.initial blocks, # delays, $display, fork-join and real arithmetic are ignored or rejected by synthesis, so RTL that simulates correctly may still not build
B.Cadence synthesis tool whose physically aware mode shares engines with Innovus so netlists are optimised against real floorplan wire loads
C.optimisation that focuses on critical paths, applying upsizing, buffering, logic restructuring and duplication to meet the clock while leaving non-critical logic small
D.synthesis optimisation letting mutually exclusive operations use one arithmetic unit through multiplexing, saving area at the cost of mux delay on the shared path
Answer + AI explanation with Pro
26. Which term means: "synthesis optimisation letting mutually exclusive operations use one arithmetic unit through multiplexing, saving area at the cost of mux delay on the shared path"?
Senior
A.Design Compiler
B.Resource sharing
C.Retiming
D.Logic synthesis
Answer + AI explanation with Pro
27. Which statement is correct?
Senior
A.Resource sharing — optimisation that focuses on critical paths, applying upsizing, buffering, logic restructuring and duplication to meet the clock while leaving non-critical logic small
B.Resource sharing — synthesis optimisation letting mutually exclusive operations use one arithmetic unit through multiplexing, saving area at the cost of mux delay on the shared path
C.Resource sharing — moving registers across combinational logic without changing function so stage delays balance, raising the achievable frequency of a pipeline
D.Resource sharing — Cadence synthesis tool whose physically aware mode shares engines with Innovus so netlists are optimised against real floorplan wire loads
Answer + AI explanation with Pro
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