27 Computer Architecture & SoC questions from the VLSI Design bank, written for Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd.
Free to start: the 2-minute ECE readiness check — six questions and a result.
A.keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
B.data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
C.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
D.ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
Answer + AI explanation with Pro
2. Which term means: "data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling"?
Junior
A.Pipeline hazards
B.RISC-V
C.AMBA bus family
D.Cache coherence
Answer + AI explanation with Pro
3. Which statement is correct?
Junior
A.Pipeline hazards — ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
B.Pipeline hazards — packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels
C.Pipeline hazards — direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
D.Pipeline hazards — data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
Answer + AI explanation with Pro
4. What is Cache mapping?
Junior
A.direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
B.data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
C.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
D.keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
Answer + AI explanation with Pro
5. Which term means: "direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time"?
Junior
A.Cache mapping
B.Memory consistency model
C.Interrupt controller
D.RISC-V
Answer + AI explanation with Pro
6. Which statement is correct?
Junior
A.Cache mapping — data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
B.Cache mapping — direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
C.Cache mapping — ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
D.Cache mapping — GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
Answer + AI explanation with Pro
7. What is AMBA bus family?
Junior
A.ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
B.direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
C.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
D.GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
Answer + AI explanation with Pro
8. Which term means: "ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic"?
Junior
A.AMBA bus family
B.Interrupt controller
C.RISC-V
D.Network-on-chip
Answer + AI explanation with Pro
9. Which statement is correct?
Junior
A.AMBA bus family — ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
B.AMBA bus family — direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
C.AMBA bus family — keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
D.AMBA bus family — rules for the order in which loads and stores become visible across cores; ARM and RISC-V are weakly ordered so software needs barriers or acquire/release semantics
Answer + AI explanation with Pro
10. What is AXI channels?
Mid
A.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
B.five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
C.data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
D.packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels
Answer + AI explanation with Pro
11. Which term means: "five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions"?
Mid
A.RISC-V
B.Network-on-chip
C.Interrupt controller
D.AXI channels
Answer + AI explanation with Pro
12. Which statement is correct?
Mid
A.AXI channels — direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
B.AXI channels — five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
C.AXI channels — keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
D.AXI channels — open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
Answer + AI explanation with Pro
13. What is Network-on-chip?
Mid
A.five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
B.packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels
C.rules for the order in which loads and stores become visible across cores; ARM and RISC-V are weakly ordered so software needs barriers or acquire/release semantics
D.GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
Answer + AI explanation with Pro
14. Which term means: "packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels"?
Mid
A.RISC-V
B.Cache mapping
C.Pipeline hazards
D.Network-on-chip
Answer + AI explanation with Pro
15. Which statement is correct?
Mid
A.Network-on-chip — ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
B.Network-on-chip — data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
C.Network-on-chip — packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels
D.Network-on-chip — rules for the order in which loads and stores become visible across cores; ARM and RISC-V are weakly ordered so software needs barriers or acquire/release semantics
Answer + AI explanation with Pro
16. What is RISC-V?
Mid
A.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
B.five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
C.GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
D.keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
Answer + AI explanation with Pro
17. Which term means: "open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions"?
Mid
A.RISC-V
B.Network-on-chip
C.Cache mapping
D.Cache coherence
Answer + AI explanation with Pro
18. Which statement is correct?
Mid
A.RISC-V — direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
B.RISC-V — packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels
C.RISC-V — keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
D.RISC-V — open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
Answer + AI explanation with Pro
19. What is Interrupt controller?
Mid
A.ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
B.GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
C.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
D.five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
Answer + AI explanation with Pro
20. Which term means: "GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling"?
Mid
A.RISC-V
B.Memory consistency model
C.Pipeline hazards
D.Interrupt controller
Answer + AI explanation with Pro
21. Which statement is correct?
Mid
A.Interrupt controller — five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
B.Interrupt controller — data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
C.Interrupt controller — ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
D.Interrupt controller — GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
Answer + AI explanation with Pro
22. What is Cache coherence?
Senior
A.keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
B.five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
C.GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
D.ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
Answer + AI explanation with Pro
23. Which term means: "keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs"?
Senior
A.AXI channels
B.Cache coherence
C.Interrupt controller
D.Pipeline hazards
Answer + AI explanation with Pro
24. Which statement is correct?
Senior
A.Cache coherence — keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
B.Cache coherence — GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
C.Cache coherence — five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
D.Cache coherence — open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
Answer + AI explanation with Pro
25. What is Memory consistency model?
Senior
A.rules for the order in which loads and stores become visible across cores; ARM and RISC-V are weakly ordered so software needs barriers or acquire/release semantics
B.ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
C.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
D.data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
Answer + AI explanation with Pro
26. Which term means: "rules for the order in which loads and stores become visible across cores; ARM and RISC-V are weakly ordered so software needs barriers or acquire/release semantics"?
Senior
A.AXI channels
B.Network-on-chip
C.Interrupt controller
D.Memory consistency model
Answer + AI explanation with Pro
27. Which statement is correct?
Senior
A.Memory consistency model — packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels
B.Memory consistency model — rules for the order in which loads and stores become visible across cores; ARM and RISC-V are weakly ordered so software needs barriers or acquire/release semantics
C.Memory consistency model — GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
D.Memory consistency model — direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
Answer + AI explanation with Pro
Free to start
Start with a free readiness check
Sign up free for the 2-minute ECE readiness check and a scored result. Answers, explanations and the AI tutor on every Computer Architecture & SoC question come with Pro.