27 Static Timing Analysis questions from the VLSI Design bank, written for Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd.
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A.timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
B.minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
C.path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
D.required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
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2. Which term means: "minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock"?
Junior
A.False path
B.On-chip variation derating
C.Setup time
D.Clock skew
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3. Which statement is correct?
Junior
A.Setup time — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
B.Setup time — minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
C.Setup time — checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
D.Setup time — OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
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4. What is Hold time?
Junior
A.timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
B.checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
C.Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation
D.minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
Answer + AI explanation with Pro
5. Which term means: "minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers"?
Junior
A.PrimeTime signoff
B.Hold time
C.Setup time
D.Multicycle path
Answer + AI explanation with Pro
6. Which statement is correct?
Junior
A.Hold time — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
B.Hold time — Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation
C.Hold time — checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
D.Hold time — required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
Answer + AI explanation with Pro
7. What is Slack?
Junior
A.checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
B.minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
C.timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
D.required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
Answer + AI explanation with Pro
8. Which term means: "required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report"?
Junior
A.Hold time
B.Multicycle path
C.Recovery and removal
D.Slack
Answer + AI explanation with Pro
9. Which statement is correct?
Junior
A.Slack — checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
B.Slack — required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
C.Slack — timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
D.Slack — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
Answer + AI explanation with Pro
10. What is Clock skew?
Mid
A.path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
B.required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
C.timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
D.difference in clock arrival between launch and capture flops; positive values help setup and hurt hold, so useful skew can be introduced deliberately
Answer + AI explanation with Pro
11. Which term means: "difference in clock arrival between launch and capture flops; positive values help setup and hurt hold, so useful skew can be introduced deliberately"?
Mid
A.Clock skew
B.Setup time
C.False path
D.PrimeTime signoff
Answer + AI explanation with Pro
12. Which statement is correct?
Mid
A.Clock skew — difference in clock arrival between launch and capture flops; positive values help setup and hurt hold, so useful skew can be introduced deliberately
B.Clock skew — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
C.Clock skew — minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
D.Clock skew — OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
Answer + AI explanation with Pro
13. What is Multicycle path?
Mid
A.path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
B.minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
C.Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation
D.minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
Answer + AI explanation with Pro
14. Which term means: "path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check"?
Mid
A.Multicycle path
B.Recovery and removal
C.Clock skew
D.Setup time
Answer + AI explanation with Pro
15. Which statement is correct?
Mid
A.Multicycle path — minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
B.Multicycle path — required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
C.Multicycle path — checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
D.Multicycle path — path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
Answer + AI explanation with Pro
16. What is False path?
Mid
A.checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
B.OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
C.timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
D.minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
Answer + AI explanation with Pro
17. Which term means: "timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation"?
Mid
A.Hold time
B.PrimeTime signoff
C.Clock skew
D.False path
Answer + AI explanation with Pro
18. Which statement is correct?
Mid
A.False path — required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
B.False path — OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
C.False path — checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
D.False path — timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
Answer + AI explanation with Pro
19. What is Recovery and removal?
Mid
A.minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
B.checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
C.OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
D.path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
Answer + AI explanation with Pro
20. Which term means: "checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases"?
Mid
A.Recovery and removal
B.Slack
C.Multicycle path
D.Clock skew
Answer + AI explanation with Pro
21. Which statement is correct?
Mid
A.Recovery and removal — path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
B.Recovery and removal — checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
C.Recovery and removal — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
D.Recovery and removal — required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
Answer + AI explanation with Pro
22. What is On-chip variation derating?
Senior
A.OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
B.path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
C.minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
D.checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
Answer + AI explanation with Pro
23. Which term means: "OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes"?
Senior
A.Setup time
B.On-chip variation derating
C.Hold time
D.Slack
Answer + AI explanation with Pro
24. Which statement is correct?
Senior
A.On-chip variation derating — difference in clock arrival between launch and capture flops; positive values help setup and hurt hold, so useful skew can be introduced deliberately
B.On-chip variation derating — Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation
C.On-chip variation derating — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
D.On-chip variation derating — OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
Answer + AI explanation with Pro
25. What is PrimeTime signoff?
Senior
A.checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
B.required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
C.Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation
D.timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
Answer + AI explanation with Pro
26. Which term means: "Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation"?
Senior
A.Multicycle path
B.Hold time
C.Slack
D.PrimeTime signoff
Answer + AI explanation with Pro
27. Which statement is correct?
Senior
A.PrimeTime signoff — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
B.PrimeTime signoff — Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation
C.PrimeTime signoff — difference in clock arrival between launch and capture flops; positive values help setup and hurt hold, so useful skew can be introduced deliberately
D.PrimeTime signoff — minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
Answer + AI explanation with Pro
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