27 RTL Design (Verilog / SystemVerilog) questions from the VLSI Design bank, written for Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd.
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1. What is Blocking versus non-blocking assignment?
Junior
A.= executes in order within a block and models combinational logic; <= schedules all updates at the end of the time step and models flip-flops, and mixing them causes simulation races
B.SystemVerilog procedural blocks that declare designer intent so synthesis and lint flag a latch inferred in a combinational block or a missing clock in a sequential one
C.unintended level-sensitive storage synthesised when a combinational block leaves a signal unassigned on some path, avoided by default assignments or full case coverage
D.state encoding with one flip-flop per state, using more registers than binary but faster next-state logic and trivial decoding, preferred on FPGAs with abundant flops
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2. Which term means: "= executes in order within a block and models combinational logic; <= schedules all updates at the end of the time step and models flip-flops, and mixing them causes simulation races"?
Junior
A.Pipelining
B.Blocking versus non-blocking assignment
C.Parameterised module
D.Clock domain crossing
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3. Which statement is correct?
Junior
A.Blocking versus non-blocking assignment — design written with parameter, localparam and generate blocks so widths and depths are chosen at instantiation, enabling reuse without editing the source
B.Blocking versus non-blocking assignment — unintended level-sensitive storage synthesised when a combinational block leaves a signal unassigned on some path, avoided by default assignments or full case coverage
C.Blocking versus non-blocking assignment — SystemVerilog procedural blocks that declare designer intent so synthesis and lint flag a latch inferred in a combinational block or a missing clock in a sequential one
D.Blocking versus non-blocking assignment — = executes in order within a block and models combinational logic; <= schedules all updates at the end of the time step and models flip-flops, and mixing them causes simulation races
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4. What is Inferred latch?
Junior
A.minimum entries to absorb a rate mismatch: for a write burst of B words drained at fr while written at fw, depth ≈ B × (1 − fr/fw), rounded up with margin for read latency
B.design written with parameter, localparam and generate blocks so widths and depths are chosen at instantiation, enabling reuse without editing the source
C.unintended level-sensitive storage synthesised when a combinational block leaves a signal unassigned on some path, avoided by default assignments or full case coverage
D.state encoding with one flip-flop per state, using more registers than binary but faster next-state logic and trivial decoding, preferred on FPGAs with abundant flops
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5. Which term means: "unintended level-sensitive storage synthesised when a combinational block leaves a signal unassigned on some path, avoided by default assignments or full case coverage"?
Junior
A.Inferred latch
B.Parameterised module
C.Blocking versus non-blocking assignment
D.Pipelining
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6. Which statement is correct?
Junior
A.Inferred latch — design written with parameter, localparam and generate blocks so widths and depths are chosen at instantiation, enabling reuse without editing the source
B.Inferred latch — state encoding with one flip-flop per state, using more registers than binary but faster next-state logic and trivial decoding, preferred on FPGAs with abundant flops
C.Inferred latch — unintended level-sensitive storage synthesised when a combinational block leaves a signal unassigned on some path, avoided by default assignments or full case coverage
D.Inferred latch — inserting registers to split a long combinational path into stages, raising clock frequency and throughput at the cost of latency and register area
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7. What is Synchronous versus asynchronous reset?
Junior
A.= executes in order within a block and models combinational logic; <= schedules all updates at the end of the time step and models flip-flops, and mixing them causes simulation races
B.minimum entries to absorb a rate mismatch: for a write burst of B words drained at fr while written at fw, depth ≈ B × (1 − fr/fw), rounded up with margin for read latency
C.transfer of a signal between unrelated clocks, needing a two-flop synchroniser for single bits, Gray-coded pointers for FIFOs and request-acknowledge handshakes for multi-bit data
D.synchronous reset is sampled at the clock edge and needs a running clock; asynchronous reset acts immediately but must be de-asserted synchronously to avoid recovery violations
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8. Which term means: "synchronous reset is sampled at the clock edge and needs a running clock; asynchronous reset acts immediately but must be de-asserted synchronously to avoid recovery violations"?
Junior
A.Pipelining
B.Blocking versus non-blocking assignment
C.FIFO depth calculation
D.Synchronous versus asynchronous reset
Answer + AI explanation with Pro
9. Which statement is correct?
Junior
A.Synchronous versus asynchronous reset — minimum entries to absorb a rate mismatch: for a write burst of B words drained at fr while written at fw, depth ≈ B × (1 − fr/fw), rounded up with margin for read latency
B.Synchronous versus asynchronous reset — synchronous reset is sampled at the clock edge and needs a running clock; asynchronous reset acts immediately but must be de-asserted synchronously to avoid recovery violations
C.Synchronous versus asynchronous reset — unintended level-sensitive storage synthesised when a combinational block leaves a signal unassigned on some path, avoided by default assignments or full case coverage
D.Synchronous versus asynchronous reset — = executes in order within a block and models combinational logic; <= schedules all updates at the end of the time step and models flip-flops, and mixing them causes simulation races
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10. What is One-hot FSM encoding?
Mid
A.state encoding with one flip-flop per state, using more registers than binary but faster next-state logic and trivial decoding, preferred on FPGAs with abundant flops
B.= executes in order within a block and models combinational logic; <= schedules all updates at the end of the time step and models flip-flops, and mixing them causes simulation races
C.transfer of a signal between unrelated clocks, needing a two-flop synchroniser for single bits, Gray-coded pointers for FIFOs and request-acknowledge handshakes for multi-bit data
D.minimum entries to absorb a rate mismatch: for a write burst of B words drained at fr while written at fw, depth ≈ B × (1 − fr/fw), rounded up with margin for read latency
Answer + AI explanation with Pro
11. Which term means: "state encoding with one flip-flop per state, using more registers than binary but faster next-state logic and trivial decoding, preferred on FPGAs with abundant flops"?
Mid
A.Pipelining
B.One-hot FSM encoding
C.Inferred latch
D.FIFO depth calculation
Answer + AI explanation with Pro
12. Which statement is correct?
Mid
A.One-hot FSM encoding — unintended level-sensitive storage synthesised when a combinational block leaves a signal unassigned on some path, avoided by default assignments or full case coverage
B.One-hot FSM encoding — state encoding with one flip-flop per state, using more registers than binary but faster next-state logic and trivial decoding, preferred on FPGAs with abundant flops
C.One-hot FSM encoding — design written with parameter, localparam and generate blocks so widths and depths are chosen at instantiation, enabling reuse without editing the source
D.One-hot FSM encoding — synchronous reset is sampled at the clock edge and needs a running clock; asynchronous reset acts immediately but must be de-asserted synchronously to avoid recovery violations
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13. What is Parameterised module?
Mid
A.= executes in order within a block and models combinational logic; <= schedules all updates at the end of the time step and models flip-flops, and mixing them causes simulation races
B.synchronous reset is sampled at the clock edge and needs a running clock; asynchronous reset acts immediately but must be de-asserted synchronously to avoid recovery violations
C.minimum entries to absorb a rate mismatch: for a write burst of B words drained at fr while written at fw, depth ≈ B × (1 − fr/fw), rounded up with margin for read latency
D.design written with parameter, localparam and generate blocks so widths and depths are chosen at instantiation, enabling reuse without editing the source
Answer + AI explanation with Pro
14. Which term means: "design written with parameter, localparam and generate blocks so widths and depths are chosen at instantiation, enabling reuse without editing the source"?
Mid
A.Clock domain crossing
B.Parameterised module
C.Blocking versus non-blocking assignment
D.One-hot FSM encoding
Answer + AI explanation with Pro
15. Which statement is correct?
Mid
A.Parameterised module — transfer of a signal between unrelated clocks, needing a two-flop synchroniser for single bits, Gray-coded pointers for FIFOs and request-acknowledge handshakes for multi-bit data
B.Parameterised module — SystemVerilog procedural blocks that declare designer intent so synthesis and lint flag a latch inferred in a combinational block or a missing clock in a sequential one
C.Parameterised module — design written with parameter, localparam and generate blocks so widths and depths are chosen at instantiation, enabling reuse without editing the source
D.Parameterised module — minimum entries to absorb a rate mismatch: for a write burst of B words drained at fr while written at fw, depth ≈ B × (1 − fr/fw), rounded up with margin for read latency
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16. What is Pipelining?
Mid
A.synchronous reset is sampled at the clock edge and needs a running clock; asynchronous reset acts immediately but must be de-asserted synchronously to avoid recovery violations
B.transfer of a signal between unrelated clocks, needing a two-flop synchroniser for single bits, Gray-coded pointers for FIFOs and request-acknowledge handshakes for multi-bit data
C.SystemVerilog procedural blocks that declare designer intent so synthesis and lint flag a latch inferred in a combinational block or a missing clock in a sequential one
D.inserting registers to split a long combinational path into stages, raising clock frequency and throughput at the cost of latency and register area
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17. Which term means: "inserting registers to split a long combinational path into stages, raising clock frequency and throughput at the cost of latency and register area"?
Mid
A.Pipelining
B.Clock domain crossing
C.Inferred latch
D.One-hot FSM encoding
Answer + AI explanation with Pro
18. Which statement is correct?
Mid
A.Pipelining — synchronous reset is sampled at the clock edge and needs a running clock; asynchronous reset acts immediately but must be de-asserted synchronously to avoid recovery violations
B.Pipelining — SystemVerilog procedural blocks that declare designer intent so synthesis and lint flag a latch inferred in a combinational block or a missing clock in a sequential one
C.Pipelining — unintended level-sensitive storage synthesised when a combinational block leaves a signal unassigned on some path, avoided by default assignments or full case coverage
D.Pipelining — inserting registers to split a long combinational path into stages, raising clock frequency and throughput at the cost of latency and register area
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19. What is always_ff and always_comb?
Mid
A.design written with parameter, localparam and generate blocks so widths and depths are chosen at instantiation, enabling reuse without editing the source
B.= executes in order within a block and models combinational logic; <= schedules all updates at the end of the time step and models flip-flops, and mixing them causes simulation races
C.minimum entries to absorb a rate mismatch: for a write burst of B words drained at fr while written at fw, depth ≈ B × (1 − fr/fw), rounded up with margin for read latency
D.SystemVerilog procedural blocks that declare designer intent so synthesis and lint flag a latch inferred in a combinational block or a missing clock in a sequential one
Answer + AI explanation with Pro
20. Which term means: "SystemVerilog procedural blocks that declare designer intent so synthesis and lint flag a latch inferred in a combinational block or a missing clock in a sequential one"?
Mid
A.One-hot FSM encoding
B.Synchronous versus asynchronous reset
C.always_ff and always_comb
D.Parameterised module
Answer + AI explanation with Pro
21. Which statement is correct?
Mid
A.always_ff and always_comb — SystemVerilog procedural blocks that declare designer intent so synthesis and lint flag a latch inferred in a combinational block or a missing clock in a sequential one
B.always_ff and always_comb — synchronous reset is sampled at the clock edge and needs a running clock; asynchronous reset acts immediately but must be de-asserted synchronously to avoid recovery violations
C.always_ff and always_comb — transfer of a signal between unrelated clocks, needing a two-flop synchroniser for single bits, Gray-coded pointers for FIFOs and request-acknowledge handshakes for multi-bit data
D.always_ff and always_comb — = executes in order within a block and models combinational logic; <= schedules all updates at the end of the time step and models flip-flops, and mixing them causes simulation races
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22. What is FIFO depth calculation?
Senior
A.state encoding with one flip-flop per state, using more registers than binary but faster next-state logic and trivial decoding, preferred on FPGAs with abundant flops
B.unintended level-sensitive storage synthesised when a combinational block leaves a signal unassigned on some path, avoided by default assignments or full case coverage
C.= executes in order within a block and models combinational logic; <= schedules all updates at the end of the time step and models flip-flops, and mixing them causes simulation races
D.minimum entries to absorb a rate mismatch: for a write burst of B words drained at fr while written at fw, depth ≈ B × (1 − fr/fw), rounded up with margin for read latency
Answer + AI explanation with Pro
23. Which term means: "minimum entries to absorb a rate mismatch: for a write burst of B words drained at fr while written at fw, depth ≈ B × (1 − fr/fw), rounded up with margin for read latency"?
Senior
A.Parameterised module
B.FIFO depth calculation
C.Blocking versus non-blocking assignment
D.Inferred latch
Answer + AI explanation with Pro
24. Which statement is correct?
Senior
A.FIFO depth calculation — design written with parameter, localparam and generate blocks so widths and depths are chosen at instantiation, enabling reuse without editing the source
B.FIFO depth calculation — = executes in order within a block and models combinational logic; <= schedules all updates at the end of the time step and models flip-flops, and mixing them causes simulation races
C.FIFO depth calculation — minimum entries to absorb a rate mismatch: for a write burst of B words drained at fr while written at fw, depth ≈ B × (1 − fr/fw), rounded up with margin for read latency
D.FIFO depth calculation — inserting registers to split a long combinational path into stages, raising clock frequency and throughput at the cost of latency and register area
Answer + AI explanation with Pro
25. What is Clock domain crossing?
Senior
A.synchronous reset is sampled at the clock edge and needs a running clock; asynchronous reset acts immediately but must be de-asserted synchronously to avoid recovery violations
B.= executes in order within a block and models combinational logic; <= schedules all updates at the end of the time step and models flip-flops, and mixing them causes simulation races
C.transfer of a signal between unrelated clocks, needing a two-flop synchroniser for single bits, Gray-coded pointers for FIFOs and request-acknowledge handshakes for multi-bit data
D.inserting registers to split a long combinational path into stages, raising clock frequency and throughput at the cost of latency and register area
Answer + AI explanation with Pro
26. Which term means: "transfer of a signal between unrelated clocks, needing a two-flop synchroniser for single bits, Gray-coded pointers for FIFOs and request-acknowledge handshakes for multi-bit data"?
Senior
A.FIFO depth calculation
B.Blocking versus non-blocking assignment
C.Clock domain crossing
D.Inferred latch
Answer + AI explanation with Pro
27. Which statement is correct?
Senior
A.Clock domain crossing — minimum entries to absorb a rate mismatch: for a write burst of B words drained at fr while written at fw, depth ≈ B × (1 − fr/fw), rounded up with margin for read latency
B.Clock domain crossing — inserting registers to split a long combinational path into stages, raising clock frequency and throughput at the cost of latency and register area
C.Clock domain crossing — transfer of a signal between unrelated clocks, needing a two-flop synchroniser for single bits, Gray-coded pointers for FIFOs and request-acknowledge handshakes for multi-bit data
D.Clock domain crossing — design written with parameter, localparam and generate blocks so widths and depths are chosen at instantiation, enabling reuse without editing the source
Answer + AI explanation with Pro
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