27 CMOS & Device Physics questions from the VLSI Design bank, written for Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd.
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A.labels such as 5 nm no longer equal any physical dimension; contacted gate pitch, metal pitch or transistor density are the honest comparators between foundries
B.voltage transfer curve whose switching threshold VM lies where both transistors saturate, placed at VDD/2 by sizing PMOS about 2–3× wider than NMOS to offset lower hole mobility
C.rise in threshold voltage when the source-to-body reverse bias grows, given by γ(√(2φF + VSB) − √(2φF)), which weakens stacked transistors and pass gates
D.sizing method that minimises path delay by equalising the effort of every stage, with the optimum stage effort near 3.6, the fan-out-of-4 rule
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2. Which term means: "voltage transfer curve whose switching threshold VM lies where both transistors saturate, placed at VDD/2 by sizing PMOS about 2–3× wider than NMOS to offset lower hole mobility"?
Junior
A.Logical effort
B.FinFET
C.CMOS inverter VTC
D.Technology node naming
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3. Which statement is correct?
Junior
A.CMOS inverter VTC — labels such as 5 nm no longer equal any physical dimension; contacted gate pitch, metal pitch or transistor density are the honest comparators between foundries
B.CMOS inverter VTC — sizing method that minimises path delay by equalising the effort of every stage, with the optimum stage effort near 3.6, the fan-out-of-4 rule
C.CMOS inverter VTC — stacked horizontal channels fully surrounded by gate, replacing fins at 3 nm and below with drive strength tuned by sheet width and near-ideal channel control
D.CMOS inverter VTC — voltage transfer curve whose switching threshold VM lies where both transistors saturate, placed at VDD/2 by sizing PMOS about 2–3× wider than NMOS to offset lower hole mobility
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4. What is Noise margin?
Junior
A.transistor with a vertical fin channel wrapped by the gate on three sides, giving stronger electrostatic control and lower leakage than planar devices from the 22 nm generation onward
B.labels such as 5 nm no longer equal any physical dimension; contacted gate pitch, metal pitch or transistor density are the honest comparators between foundries
C.NMH = VOH − VIH and NML = VIL − VOL, the input noise a gate tolerates before its output leaves valid logic levels, measured at the unity-gain points of the transfer curve
D.rise in threshold voltage when the source-to-body reverse bias grows, given by γ(√(2φF + VSB) − √(2φF)), which weakens stacked transistors and pass gates
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5. Which term means: "NMH = VOH − VIH and NML = VIL − VOL, the input noise a gate tolerates before its output leaves valid logic levels, measured at the unity-gain points of the transfer curve"?
Junior
A.CMOS inverter VTC
B.Noise margin
C.Logical effort
D.Body effect
Answer + AI explanation with Pro
6. Which statement is correct?
Junior
A.Noise margin — labels such as 5 nm no longer equal any physical dimension; contacted gate pitch, metal pitch or transistor density are the honest comparators between foundries
B.Noise margin — transistor with a vertical fin channel wrapped by the gate on three sides, giving stronger electrostatic control and lower leakage than planar devices from the 22 nm generation onward
C.Noise margin — voltage transfer curve whose switching threshold VM lies where both transistors saturate, placed at VDD/2 by sizing PMOS about 2–3× wider than NMOS to offset lower hole mobility
D.Noise margin — NMH = VOH − VIH and NML = VIL − VOL, the input noise a gate tolerates before its output leaves valid logic levels, measured at the unity-gain points of the transfer curve
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7. What is Body effect?
Junior
A.NMH = VOH − VIH and NML = VIL − VOL, the input noise a gate tolerates before its output leaves valid logic levels, measured at the unity-gain points of the transfer curve
B.stacked horizontal channels fully surrounded by gate, replacing fins at 3 nm and below with drive strength tuned by sheet width and near-ideal channel control
C.rise in threshold voltage when the source-to-body reverse bias grows, given by γ(√(2φF + VSB) − √(2φF)), which weakens stacked transistors and pass gates
D.transistor with a vertical fin channel wrapped by the gate on three sides, giving stronger electrostatic control and lower leakage than planar devices from the 22 nm generation onward
Answer + AI explanation with Pro
8. Which term means: "rise in threshold voltage when the source-to-body reverse bias grows, given by γ(√(2φF + VSB) − √(2φF)), which weakens stacked transistors and pass gates"?
Junior
A.FinFET
B.Subthreshold leakage
C.Technology node naming
D.Body effect
Answer + AI explanation with Pro
9. Which statement is correct?
Junior
A.Body effect — transistor with a vertical fin channel wrapped by the gate on three sides, giving stronger electrostatic control and lower leakage than planar devices from the 22 nm generation onward
B.Body effect — rise in threshold voltage when the source-to-body reverse bias grows, given by γ(√(2φF + VSB) − √(2φF)), which weakens stacked transistors and pass gates
C.Body effect — sizing method that minimises path delay by equalising the effort of every stage, with the optimum stage effort near 3.6, the fan-out-of-4 rule
D.Body effect — NMH = VOH − VIH and NML = VIL − VOL, the input noise a gate tolerates before its output leaves valid logic levels, measured at the unity-gain points of the transfer curve
Answer + AI explanation with Pro
10. What is Short-channel effects?
Mid
A.sizing method that minimises path delay by equalising the effort of every stage, with the optimum stage effort near 3.6, the fan-out-of-4 rule
B.labels such as 5 nm no longer equal any physical dimension; contacted gate pitch, metal pitch or transistor density are the honest comparators between foundries
C.drain-induced barrier lowering, velocity saturation and threshold roll-off that appear when channel length approaches depletion widths, raising leakage and weakening gate control
D.stacked horizontal channels fully surrounded by gate, replacing fins at 3 nm and below with drive strength tuned by sheet width and near-ideal channel control
Answer + AI explanation with Pro
11. Which term means: "drain-induced barrier lowering, velocity saturation and threshold roll-off that appear when channel length approaches depletion widths, raising leakage and weakening gate control"?
Mid
A.Gate-all-around nanosheet
B.Short-channel effects
C.Subthreshold leakage
D.CMOS inverter VTC
Answer + AI explanation with Pro
12. Which statement is correct?
Mid
A.Short-channel effects — NMH = VOH − VIH and NML = VIL − VOL, the input noise a gate tolerates before its output leaves valid logic levels, measured at the unity-gain points of the transfer curve
B.Short-channel effects — rise in threshold voltage when the source-to-body reverse bias grows, given by γ(√(2φF + VSB) − √(2φF)), which weakens stacked transistors and pass gates
C.Short-channel effects — drain-induced barrier lowering, velocity saturation and threshold roll-off that appear when channel length approaches depletion widths, raising leakage and weakening gate control
D.Short-channel effects — stacked horizontal channels fully surrounded by gate, replacing fins at 3 nm and below with drive strength tuned by sheet width and near-ideal channel control
Answer + AI explanation with Pro
13. What is Subthreshold leakage?
Mid
A.drain current below threshold falling exponentially with gate voltage at about 60–100 mV per decade, the dominant static power component below 90 nm
B.rise in threshold voltage when the source-to-body reverse bias grows, given by γ(√(2φF + VSB) − √(2φF)), which weakens stacked transistors and pass gates
C.drain-induced barrier lowering, velocity saturation and threshold roll-off that appear when channel length approaches depletion widths, raising leakage and weakening gate control
D.voltage transfer curve whose switching threshold VM lies where both transistors saturate, placed at VDD/2 by sizing PMOS about 2–3× wider than NMOS to offset lower hole mobility
Answer + AI explanation with Pro
14. Which term means: "drain current below threshold falling exponentially with gate voltage at about 60–100 mV per decade, the dominant static power component below 90 nm"?
Mid
A.Logical effort
B.Short-channel effects
C.Subthreshold leakage
D.Noise margin
Answer + AI explanation with Pro
15. Which statement is correct?
Mid
A.Subthreshold leakage — voltage transfer curve whose switching threshold VM lies where both transistors saturate, placed at VDD/2 by sizing PMOS about 2–3× wider than NMOS to offset lower hole mobility
B.Subthreshold leakage — drain current below threshold falling exponentially with gate voltage at about 60–100 mV per decade, the dominant static power component below 90 nm
C.Subthreshold leakage — NMH = VOH − VIH and NML = VIL − VOL, the input noise a gate tolerates before its output leaves valid logic levels, measured at the unity-gain points of the transfer curve
D.Subthreshold leakage — drain-induced barrier lowering, velocity saturation and threshold roll-off that appear when channel length approaches depletion widths, raising leakage and weakening gate control
Answer + AI explanation with Pro
16. What is FinFET?
Mid
A.voltage transfer curve whose switching threshold VM lies where both transistors saturate, placed at VDD/2 by sizing PMOS about 2–3× wider than NMOS to offset lower hole mobility
B.transistor with a vertical fin channel wrapped by the gate on three sides, giving stronger electrostatic control and lower leakage than planar devices from the 22 nm generation onward
C.NMH = VOH − VIH and NML = VIL − VOL, the input noise a gate tolerates before its output leaves valid logic levels, measured at the unity-gain points of the transfer curve
D.rise in threshold voltage when the source-to-body reverse bias grows, given by γ(√(2φF + VSB) − √(2φF)), which weakens stacked transistors and pass gates
Answer + AI explanation with Pro
17. Which term means: "transistor with a vertical fin channel wrapped by the gate on three sides, giving stronger electrostatic control and lower leakage than planar devices from the 22 nm generation onward"?
Mid
A.Body effect
B.Logical effort
C.Short-channel effects
D.FinFET
Answer + AI explanation with Pro
18. Which statement is correct?
Mid
A.FinFET — drain-induced barrier lowering, velocity saturation and threshold roll-off that appear when channel length approaches depletion widths, raising leakage and weakening gate control
B.FinFET — transistor with a vertical fin channel wrapped by the gate on three sides, giving stronger electrostatic control and lower leakage than planar devices from the 22 nm generation onward
C.FinFET — NMH = VOH − VIH and NML = VIL − VOL, the input noise a gate tolerates before its output leaves valid logic levels, measured at the unity-gain points of the transfer curve
D.FinFET — stacked horizontal channels fully surrounded by gate, replacing fins at 3 nm and below with drive strength tuned by sheet width and near-ideal channel control
Answer + AI explanation with Pro
19. What is Gate-all-around nanosheet?
Mid
A.rise in threshold voltage when the source-to-body reverse bias grows, given by γ(√(2φF + VSB) − √(2φF)), which weakens stacked transistors and pass gates
B.labels such as 5 nm no longer equal any physical dimension; contacted gate pitch, metal pitch or transistor density are the honest comparators between foundries
C.stacked horizontal channels fully surrounded by gate, replacing fins at 3 nm and below with drive strength tuned by sheet width and near-ideal channel control
D.drain-induced barrier lowering, velocity saturation and threshold roll-off that appear when channel length approaches depletion widths, raising leakage and weakening gate control
Answer + AI explanation with Pro
20. Which term means: "stacked horizontal channels fully surrounded by gate, replacing fins at 3 nm and below with drive strength tuned by sheet width and near-ideal channel control"?
Mid
A.Body effect
B.Logical effort
C.Subthreshold leakage
D.Gate-all-around nanosheet
Answer + AI explanation with Pro
21. Which statement is correct?
Mid
A.Gate-all-around nanosheet — stacked horizontal channels fully surrounded by gate, replacing fins at 3 nm and below with drive strength tuned by sheet width and near-ideal channel control
B.Gate-all-around nanosheet — NMH = VOH − VIH and NML = VIL − VOL, the input noise a gate tolerates before its output leaves valid logic levels, measured at the unity-gain points of the transfer curve
C.Gate-all-around nanosheet — rise in threshold voltage when the source-to-body reverse bias grows, given by γ(√(2φF + VSB) − √(2φF)), which weakens stacked transistors and pass gates
D.Gate-all-around nanosheet — drain current below threshold falling exponentially with gate voltage at about 60–100 mV per decade, the dominant static power component below 90 nm
Answer + AI explanation with Pro
22. What is Logical effort?
Senior
A.drain current below threshold falling exponentially with gate voltage at about 60–100 mV per decade, the dominant static power component below 90 nm
B.NMH = VOH − VIH and NML = VIL − VOL, the input noise a gate tolerates before its output leaves valid logic levels, measured at the unity-gain points of the transfer curve
C.sizing method that minimises path delay by equalising the effort of every stage, with the optimum stage effort near 3.6, the fan-out-of-4 rule
D.rise in threshold voltage when the source-to-body reverse bias grows, given by γ(√(2φF + VSB) − √(2φF)), which weakens stacked transistors and pass gates
Answer + AI explanation with Pro
23. Which term means: "sizing method that minimises path delay by equalising the effort of every stage, with the optimum stage effort near 3.6, the fan-out-of-4 rule"?
Senior
A.Noise margin
B.Short-channel effects
C.Logical effort
D.Technology node naming
Answer + AI explanation with Pro
24. Which statement is correct?
Senior
A.Logical effort — stacked horizontal channels fully surrounded by gate, replacing fins at 3 nm and below with drive strength tuned by sheet width and near-ideal channel control
B.Logical effort — sizing method that minimises path delay by equalising the effort of every stage, with the optimum stage effort near 3.6, the fan-out-of-4 rule
C.Logical effort — transistor with a vertical fin channel wrapped by the gate on three sides, giving stronger electrostatic control and lower leakage than planar devices from the 22 nm generation onward
D.Logical effort — labels such as 5 nm no longer equal any physical dimension; contacted gate pitch, metal pitch or transistor density are the honest comparators between foundries
Answer + AI explanation with Pro
25. What is Technology node naming?
Senior
A.labels such as 5 nm no longer equal any physical dimension; contacted gate pitch, metal pitch or transistor density are the honest comparators between foundries
B.drain current below threshold falling exponentially with gate voltage at about 60–100 mV per decade, the dominant static power component below 90 nm
C.transistor with a vertical fin channel wrapped by the gate on three sides, giving stronger electrostatic control and lower leakage than planar devices from the 22 nm generation onward
D.voltage transfer curve whose switching threshold VM lies where both transistors saturate, placed at VDD/2 by sizing PMOS about 2–3× wider than NMOS to offset lower hole mobility
Answer + AI explanation with Pro
26. Which term means: "labels such as 5 nm no longer equal any physical dimension; contacted gate pitch, metal pitch or transistor density are the honest comparators between foundries"?
Senior
A.FinFET
B.Technology node naming
C.Gate-all-around nanosheet
D.Subthreshold leakage
Answer + AI explanation with Pro
27. Which statement is correct?
Senior
A.Technology node naming — drain-induced barrier lowering, velocity saturation and threshold roll-off that appear when channel length approaches depletion widths, raising leakage and weakening gate control
B.Technology node naming — drain current below threshold falling exponentially with gate voltage at about 60–100 mV per decade, the dominant static power component below 90 nm
C.Technology node naming — rise in threshold voltage when the source-to-body reverse bias grows, given by γ(√(2φF + VSB) − √(2φF)), which weakens stacked transistors and pass gates
D.Technology node naming — labels such as 5 nm no longer equal any physical dimension; contacted gate pitch, metal pitch or transistor density are the honest comparators between foundries
Answer + AI explanation with Pro
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