27 DFT questions from the VLSI Design bank, written for Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd.
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A.register of cells at every I/O pin, controlled through the TAP, used to test board-level interconnect and program devices without physical probing
B.flip-flops replaced by scan cells stitched into shift registers so any state can be loaded and observed through a few pins, turning sequential test into combinational
C.on-chip decompressor and compactor letting a few scan pins drive hundreds of internal chains, cutting test time and data volume 50–100×
D.slow-to-rise or slow-to-fall model tested with launch-on-capture or launch-on-shift at-speed patterns, needed because stuck-at misses timing defects
Answer + AI explanation with Pro
2. Which term means: "flip-flops replaced by scan cells stitched into shift registers so any state can be loaded and observed through a few pins, turning sequential test into combinational"?
Junior
A.Test compression
B.Logic BIST
C.Scan chain
D.Stuck-at fault model
Answer + AI explanation with Pro
3. Which statement is correct?
Junior
A.Scan chain — register of cells at every I/O pin, controlled through the TAP, used to test board-level interconnect and program devices without physical probing
B.Scan chain — flip-flops replaced by scan cells stitched into shift registers so any state can be loaded and observed through a few pins, turning sequential test into combinational
C.Scan chain — test access port with TDI, TDO, TCK, TMS and optional TRST, a 16-state TAP controller and mandatory instructions BYPASS, EXTEST and SAMPLE/PRELOAD
D.Scan chain — assumes a net is permanently 0 or 1; coverage of 98–99% is the usual production target because the model catches most manufacturing defects cheaply
Answer + AI explanation with Pro
4. What is Stuck-at fault model?
Junior
A.assumes a net is permanently 0 or 1; coverage of 98–99% is the usual production target because the model catches most manufacturing defects cheaply
B.flip-flops replaced by scan cells stitched into shift registers so any state can be loaded and observed through a few pins, turning sequential test into combinational
C.on-chip controller running March algorithms such as March C- on embedded SRAMs at speed, reporting failures and driving repair via redundant rows or columns
D.slow-to-rise or slow-to-fall model tested with launch-on-capture or launch-on-shift at-speed patterns, needed because stuck-at misses timing defects
Answer + AI explanation with Pro
5. Which term means: "assumes a net is permanently 0 or 1; coverage of 98–99% is the usual production target because the model catches most manufacturing defects cheaply"?
Junior
A.Stuck-at fault model
B.Scan chain
C.Test compression
D.Transition delay fault
Answer + AI explanation with Pro
6. Which statement is correct?
Junior
A.Stuck-at fault model — slow-to-rise or slow-to-fall model tested with launch-on-capture or launch-on-shift at-speed patterns, needed because stuck-at misses timing defects
B.Stuck-at fault model — register of cells at every I/O pin, controlled through the TAP, used to test board-level interconnect and program devices without physical probing
C.Stuck-at fault model — assumes a net is permanently 0 or 1; coverage of 98–99% is the usual production target because the model catches most manufacturing defects cheaply
D.Stuck-at fault model — on-chip decompressor and compactor letting a few scan pins drive hundreds of internal chains, cutting test time and data volume 50–100×
Answer + AI explanation with Pro
7. What is JTAG IEEE 1149.1?
Junior
A.flip-flops replaced by scan cells stitched into shift registers so any state can be loaded and observed through a few pins, turning sequential test into combinational
B.register of cells at every I/O pin, controlled through the TAP, used to test board-level interconnect and program devices without physical probing
C.on-chip controller running March algorithms such as March C- on embedded SRAMs at speed, reporting failures and driving repair via redundant rows or columns
D.test access port with TDI, TDO, TCK, TMS and optional TRST, a 16-state TAP controller and mandatory instructions BYPASS, EXTEST and SAMPLE/PRELOAD
Answer + AI explanation with Pro
8. Which term means: "test access port with TDI, TDO, TCK, TMS and optional TRST, a 16-state TAP controller and mandatory instructions BYPASS, EXTEST and SAMPLE/PRELOAD"?
Junior
A.Logic BIST
B.JTAG IEEE 1149.1
C.Scan chain
D.Transition delay fault
Answer + AI explanation with Pro
9. Which statement is correct?
Junior
A.JTAG IEEE 1149.1 — test access port with TDI, TDO, TCK, TMS and optional TRST, a 16-state TAP controller and mandatory instructions BYPASS, EXTEST and SAMPLE/PRELOAD
B.JTAG IEEE 1149.1 — on-chip decompressor and compactor letting a few scan pins drive hundreds of internal chains, cutting test time and data volume 50–100×
C.JTAG IEEE 1149.1 — automatic pattern generation that sensitises a fault, propagates its effect to a scan output and justifies the inputs, with tools such as TetraMAX or Tessent
D.JTAG IEEE 1149.1 — flip-flops replaced by scan cells stitched into shift registers so any state can be loaded and observed through a few pins, turning sequential test into combinational
Answer + AI explanation with Pro
10. What is Transition delay fault?
Mid
A.register of cells at every I/O pin, controlled through the TAP, used to test board-level interconnect and program devices without physical probing
B.assumes a net is permanently 0 or 1; coverage of 98–99% is the usual production target because the model catches most manufacturing defects cheaply
C.slow-to-rise or slow-to-fall model tested with launch-on-capture or launch-on-shift at-speed patterns, needed because stuck-at misses timing defects
D.pseudo-random patterns from an LFSR applied through scan and compressed into a MISR signature, enabling in-field self-test demanded by ISO 26262
Answer + AI explanation with Pro
11. Which term means: "slow-to-rise or slow-to-fall model tested with launch-on-capture or launch-on-shift at-speed patterns, needed because stuck-at misses timing defects"?
Mid
A.Stuck-at fault model
B.Test compression
C.Logic BIST
D.Transition delay fault
Answer + AI explanation with Pro
12. Which statement is correct?
Mid
A.Transition delay fault — slow-to-rise or slow-to-fall model tested with launch-on-capture or launch-on-shift at-speed patterns, needed because stuck-at misses timing defects
B.Transition delay fault — on-chip controller running March algorithms such as March C- on embedded SRAMs at speed, reporting failures and driving repair via redundant rows or columns
C.Transition delay fault — test access port with TDI, TDO, TCK, TMS and optional TRST, a 16-state TAP controller and mandatory instructions BYPASS, EXTEST and SAMPLE/PRELOAD
D.Transition delay fault — pseudo-random patterns from an LFSR applied through scan and compressed into a MISR signature, enabling in-field self-test demanded by ISO 26262
Answer + AI explanation with Pro
13. What is ATPG?
Mid
A.automatic pattern generation that sensitises a fault, propagates its effect to a scan output and justifies the inputs, with tools such as TetraMAX or Tessent
B.assumes a net is permanently 0 or 1; coverage of 98–99% is the usual production target because the model catches most manufacturing defects cheaply
C.slow-to-rise or slow-to-fall model tested with launch-on-capture or launch-on-shift at-speed patterns, needed because stuck-at misses timing defects
D.register of cells at every I/O pin, controlled through the TAP, used to test board-level interconnect and program devices without physical probing
Answer + AI explanation with Pro
14. Which term means: "automatic pattern generation that sensitises a fault, propagates its effect to a scan output and justifies the inputs, with tools such as TetraMAX or Tessent"?
Mid
A.ATPG
B.Boundary scan
C.Logic BIST
D.Transition delay fault
Answer + AI explanation with Pro
15. Which statement is correct?
Mid
A.ATPG — test access port with TDI, TDO, TCK, TMS and optional TRST, a 16-state TAP controller and mandatory instructions BYPASS, EXTEST and SAMPLE/PRELOAD
B.ATPG — on-chip controller running March algorithms such as March C- on embedded SRAMs at speed, reporting failures and driving repair via redundant rows or columns
C.ATPG — assumes a net is permanently 0 or 1; coverage of 98–99% is the usual production target because the model catches most manufacturing defects cheaply
D.ATPG — automatic pattern generation that sensitises a fault, propagates its effect to a scan output and justifies the inputs, with tools such as TetraMAX or Tessent
Answer + AI explanation with Pro
16. What is Test compression?
Mid
A.assumes a net is permanently 0 or 1; coverage of 98–99% is the usual production target because the model catches most manufacturing defects cheaply
B.flip-flops replaced by scan cells stitched into shift registers so any state can be loaded and observed through a few pins, turning sequential test into combinational
C.on-chip decompressor and compactor letting a few scan pins drive hundreds of internal chains, cutting test time and data volume 50–100×
D.automatic pattern generation that sensitises a fault, propagates its effect to a scan output and justifies the inputs, with tools such as TetraMAX or Tessent
Answer + AI explanation with Pro
17. Which term means: "on-chip decompressor and compactor letting a few scan pins drive hundreds of internal chains, cutting test time and data volume 50–100×"?
Mid
A.Test compression
B.Memory BIST
C.Stuck-at fault model
D.Scan chain
Answer + AI explanation with Pro
18. Which statement is correct?
Mid
A.Test compression — slow-to-rise or slow-to-fall model tested with launch-on-capture or launch-on-shift at-speed patterns, needed because stuck-at misses timing defects
B.Test compression — test access port with TDI, TDO, TCK, TMS and optional TRST, a 16-state TAP controller and mandatory instructions BYPASS, EXTEST and SAMPLE/PRELOAD
C.Test compression — on-chip decompressor and compactor letting a few scan pins drive hundreds of internal chains, cutting test time and data volume 50–100×
D.Test compression — on-chip controller running March algorithms such as March C- on embedded SRAMs at speed, reporting failures and driving repair via redundant rows or columns
Answer + AI explanation with Pro
19. What is Boundary scan?
Mid
A.slow-to-rise or slow-to-fall model tested with launch-on-capture or launch-on-shift at-speed patterns, needed because stuck-at misses timing defects
B.register of cells at every I/O pin, controlled through the TAP, used to test board-level interconnect and program devices without physical probing
C.automatic pattern generation that sensitises a fault, propagates its effect to a scan output and justifies the inputs, with tools such as TetraMAX or Tessent
D.on-chip controller running March algorithms such as March C- on embedded SRAMs at speed, reporting failures and driving repair via redundant rows or columns
Answer + AI explanation with Pro
20. Which term means: "register of cells at every I/O pin, controlled through the TAP, used to test board-level interconnect and program devices without physical probing"?
Mid
A.Logic BIST
B.Test compression
C.Boundary scan
D.Scan chain
Answer + AI explanation with Pro
21. Which statement is correct?
Mid
A.Boundary scan — test access port with TDI, TDO, TCK, TMS and optional TRST, a 16-state TAP controller and mandatory instructions BYPASS, EXTEST and SAMPLE/PRELOAD
B.Boundary scan — register of cells at every I/O pin, controlled through the TAP, used to test board-level interconnect and program devices without physical probing
C.Boundary scan — automatic pattern generation that sensitises a fault, propagates its effect to a scan output and justifies the inputs, with tools such as TetraMAX or Tessent
D.Boundary scan — assumes a net is permanently 0 or 1; coverage of 98–99% is the usual production target because the model catches most manufacturing defects cheaply
Answer + AI explanation with Pro
22. What is Memory BIST?
Mid
A.on-chip decompressor and compactor letting a few scan pins drive hundreds of internal chains, cutting test time and data volume 50–100×
B.on-chip controller running March algorithms such as March C- on embedded SRAMs at speed, reporting failures and driving repair via redundant rows or columns
C.automatic pattern generation that sensitises a fault, propagates its effect to a scan output and justifies the inputs, with tools such as TetraMAX or Tessent
D.pseudo-random patterns from an LFSR applied through scan and compressed into a MISR signature, enabling in-field self-test demanded by ISO 26262
Answer + AI explanation with Pro
23. Which term means: "on-chip controller running March algorithms such as March C- on embedded SRAMs at speed, reporting failures and driving repair via redundant rows or columns"?
Mid
A.Logic BIST
B.JTAG IEEE 1149.1
C.Memory BIST
D.Scan chain
Answer + AI explanation with Pro
24. Which statement is correct?
Mid
A.Memory BIST — on-chip controller running March algorithms such as March C- on embedded SRAMs at speed, reporting failures and driving repair via redundant rows or columns
B.Memory BIST — pseudo-random patterns from an LFSR applied through scan and compressed into a MISR signature, enabling in-field self-test demanded by ISO 26262
C.Memory BIST — flip-flops replaced by scan cells stitched into shift registers so any state can be loaded and observed through a few pins, turning sequential test into combinational
D.Memory BIST — register of cells at every I/O pin, controlled through the TAP, used to test board-level interconnect and program devices without physical probing
Answer + AI explanation with Pro
25. What is Logic BIST?
Senior
A.pseudo-random patterns from an LFSR applied through scan and compressed into a MISR signature, enabling in-field self-test demanded by ISO 26262
B.test access port with TDI, TDO, TCK, TMS and optional TRST, a 16-state TAP controller and mandatory instructions BYPASS, EXTEST and SAMPLE/PRELOAD
C.on-chip controller running March algorithms such as March C- on embedded SRAMs at speed, reporting failures and driving repair via redundant rows or columns
D.slow-to-rise or slow-to-fall model tested with launch-on-capture or launch-on-shift at-speed patterns, needed because stuck-at misses timing defects
Answer + AI explanation with Pro
26. Which term means: "pseudo-random patterns from an LFSR applied through scan and compressed into a MISR signature, enabling in-field self-test demanded by ISO 26262"?
Senior
A.Test compression
B.Transition delay fault
C.Memory BIST
D.Logic BIST
Answer + AI explanation with Pro
27. Which statement is correct?
Senior
A.Logic BIST — on-chip controller running March algorithms such as March C- on embedded SRAMs at speed, reporting failures and driving repair via redundant rows or columns
B.Logic BIST — flip-flops replaced by scan cells stitched into shift registers so any state can be loaded and observed through a few pins, turning sequential test into combinational
C.Logic BIST — automatic pattern generation that sensitises a fault, propagates its effect to a scan output and justifies the inputs, with tools such as TetraMAX or Tessent
D.Logic BIST — pseudo-random patterns from an LFSR applied through scan and compressed into a MISR signature, enabling in-field self-test demanded by ISO 26262
Answer + AI explanation with Pro
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