Verification (UVM) interview questions

1. A.user-defined covergroups, coverpoints and crosses tied to the verification plan, measuring whether specified scenarios occurred rather than which code ran
2. B.immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
3. C.IEEE 1800.2 class library structuring a testbench as test, environment and agents with sequencer, driver and monitor, connected by TLM ports and a config database
4. D.ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends

Answer + AI explanation with Pro

1. A.UVM phasing
2. B.UVM testbench layering
3. C.SystemVerilog assertions
4. D.Verification IP

Answer + AI explanation with Pro

1. A.UVM testbench layering — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
2. B.UVM testbench layering — pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
3. C.UVM testbench layering — sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
4. D.UVM testbench layering — IEEE 1800.2 class library structuring a testbench as test, environment and agents with sequencer, driver and monitor, connected by TLM ports and a config database

Answer + AI explanation with Pro

1. A.tool-collected line, toggle, branch, condition and FSM metrics showing which RTL was exercised, necessary but not sufficient for closure
2. B.component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness
3. C.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
4. D.generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss

Answer + AI explanation with Pro

1. A.UVM phasing
2. B.Verification IP
3. C.Constrained random verification
4. D.Scoreboard

Answer + AI explanation with Pro

1. A.Constrained random verification — IEEE 1800.2 class library structuring a testbench as test, environment and agents with sequencer, driver and monitor, connected by TLM ports and a config database
2. B.Constrained random verification — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
3. C.Constrained random verification — immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
4. D.Constrained random verification — user-defined covergroups, coverpoints and crosses tied to the verification plan, measuring whether specified scenarios occurred rather than which code ran

Answer + AI explanation with Pro

1. A.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
2. B.immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
3. C.tool-collected line, toggle, branch, condition and FSM metrics showing which RTL was exercised, necessary but not sufficient for closure
4. D.component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness

Answer + AI explanation with Pro

1. A.Scoreboard
2. B.UVM phasing
3. C.UVM sequence and sequencer
4. D.Code coverage

Answer + AI explanation with Pro

1. A.Code coverage — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
2. B.Code coverage — tool-collected line, toggle, branch, condition and FSM metrics showing which RTL was exercised, necessary but not sufficient for closure
3. C.Code coverage — pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
4. D.Code coverage — component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness

Answer + AI explanation with Pro

1. A.generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
2. B.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
3. C.user-defined covergroups, coverpoints and crosses tied to the verification plan, measuring whether specified scenarios occurred rather than which code ran
4. D.immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal

Answer + AI explanation with Pro

1. A.Verification IP
2. B.Constrained random verification
3. C.Functional coverage
4. D.Code coverage

Answer + AI explanation with Pro

1. A.Functional coverage — pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
2. B.Functional coverage — immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
3. C.Functional coverage — user-defined covergroups, coverpoints and crosses tied to the verification plan, measuring whether specified scenarios occurred rather than which code ran
4. D.Functional coverage — sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake

Answer + AI explanation with Pro

1. A.generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
2. B.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
3. C.component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness
4. D.immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal

Answer + AI explanation with Pro

1. A.Code coverage
2. B.Constrained random verification
3. C.Scoreboard
4. D.Verification IP

Answer + AI explanation with Pro

1. A.Scoreboard — sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
2. B.Scoreboard — ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends
3. C.Scoreboard — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
4. D.Scoreboard — component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness

Answer + AI explanation with Pro

1. A.tool-collected line, toggle, branch, condition and FSM metrics showing which RTL was exercised, necessary but not sufficient for closure
2. B.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
3. C.pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
4. D.ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends

Answer + AI explanation with Pro

1. A.UVM phasing
2. B.UVM sequence and sequencer
3. C.Scoreboard
4. D.SystemVerilog assertions

Answer + AI explanation with Pro

1. A.UVM sequence and sequencer — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
2. B.UVM sequence and sequencer — user-defined covergroups, coverpoints and crosses tied to the verification plan, measuring whether specified scenarios occurred rather than which code ran
3. C.UVM sequence and sequencer — sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
4. D.UVM sequence and sequencer — ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends

Answer + AI explanation with Pro

1. A.IEEE 1800.2 class library structuring a testbench as test, environment and agents with sequencer, driver and monitor, connected by TLM ports and a config database
2. B.generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
3. C.pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
4. D.immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal

Answer + AI explanation with Pro

1. A.Functional coverage
2. B.Constrained random verification
3. C.Code coverage
4. D.SystemVerilog assertions

Answer + AI explanation with Pro

1. A.SystemVerilog assertions — ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends
2. B.SystemVerilog assertions — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
3. C.SystemVerilog assertions — component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness
4. D.SystemVerilog assertions — immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal

Answer + AI explanation with Pro

1. A.immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
2. B.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
3. C.pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
4. D.IEEE 1800.2 class library structuring a testbench as test, environment and agents with sequencer, driver and monitor, connected by TLM ports and a config database

Answer + AI explanation with Pro

1. A.Constrained random verification
2. B.Functional coverage
3. C.UVM phasing
4. D.Verification IP

Answer + AI explanation with Pro

1. A.Verification IP — ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends
2. B.Verification IP — tool-collected line, toggle, branch, condition and FSM metrics showing which RTL was exercised, necessary but not sufficient for closure
3. C.Verification IP — component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness
4. D.Verification IP — pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers

Answer + AI explanation with Pro

1. A.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
2. B.pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
3. C.ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends
4. D.tool-collected line, toggle, branch, condition and FSM metrics showing which RTL was exercised, necessary but not sufficient for closure

Answer + AI explanation with Pro

1. A.UVM phasing
2. B.Functional coverage
3. C.Code coverage
4. D.UVM sequence and sequencer

Answer + AI explanation with Pro

1. A.UVM phasing — component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness
2. B.UVM phasing — IEEE 1800.2 class library structuring a testbench as test, environment and agents with sequencer, driver and monitor, connected by TLM ports and a config database
3. C.UVM phasing — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
4. D.UVM phasing — ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends

Answer + AI explanation with Pro